| Message ID | 1371712491-31070-1-git-send-email-jagarwal@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06/20/2013 01:14 AM, Jay Agarwal wrote: > - decrease non-prefetch memory size to 128 MB > - increase prefetch memory size to 384 MB > - above change is done because most pcie devices > prefetch memory size requirement is quite higher > compared to non-prefetch memory space. It's possible this change won't be suitable for all applications. People may simply need to adjust their DT based on what they want to connect. Still, this patch probably biases things in the correct way for now. Longer term, we might want to investigate dynamically sizing the windows in order to support arbitrary attached devices, in much the same way as the Marvell code does/will in order to conserve physical/bus address space for their multiple controllers. However, this change allows me to correctly enumerate a particular GPU I have plugged into my Harmony board, and assign all the BARs, so: Tested-by: Stephen Warren <swarren@nvidia.com>
> On 06/20/2013 01:14 AM, Jay Agarwal wrote: > > - decrease non-prefetch memory size to 128 MB > > - increase prefetch memory size to 384 MB > > - above change is done because most pcie devices > > prefetch memory size requirement is quite higher > > compared to non-prefetch memory space. > > It's possible this change won't be suitable for all applications. People may > simply need to adjust their DT based on what they want to connect. > Still, this patch probably biases things in the correct way for now. > Longer term, we might want to investigate dynamically sizing the windows > in order to support arbitrary attached devices, in much the same way as the > Marvell code does/will in order to conserve physical/bus address space for > their multiple controllers. > > However, this change allows me to correctly enumerate a particular GPU I > have plugged into my Harmony board, and assign all the BARs, so: > > Tested-by: Stephen Warren <swarren@nvidia.com> > Thierry, Could you please integrate this change also to your branch if review is done. Please let me know once it is done.
On 06/20/2013 11:30 PM, Jay Agarwal wrote: >> On 06/20/2013 01:14 AM, Jay Agarwal wrote: >>> - decrease non-prefetch memory size to 128 MB >>> - increase prefetch memory size to 384 MB >>> - above change is done because most pcie devices >>> prefetch memory size requirement is quite higher >>> compared to non-prefetch memory space. >> >> It's possible this change won't be suitable for all applications. People may >> simply need to adjust their DT based on what they want to connect. >> Still, this patch probably biases things in the correct way for now. >> Longer term, we might want to investigate dynamically sizing the windows >> in order to support arbitrary attached devices, in much the same way as the >> Marvell code does/will in order to conserve physical/bus address space for >> their multiple controllers. >> >> However, this change allows me to correctly enumerate a particular GPU I >> have plugged into my Harmony board, and assign all the BARs, so: >> >> Tested-by: Stephen Warren <swarren@nvidia.com> > > Thierry, > Could you please integrate this change also to your branch if review is done. Please let me know once it is done. I'm sure he will, but pinging after less than 24 hours is a little quick.
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index fd2a7e1..e09e97f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -483,8 +483,8 @@ ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ - 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ + 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>, <&tegra_car 118>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index e0b96bd..b02bbb4 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -35,8 +35,8 @@ 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ - 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ + 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>, <&tegra_car 118>, <&tegra_car 215>;
- decrease non-prefetch memory size to 128 MB - increase prefetch memory size to 384 MB - above change is done because most pcie devices prefetch memory size requirement is quite higher compared to non-prefetch memory space. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> --- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should be applied on top of this arch/arm/boot/dts/tegra20.dtsi | 4 ++-- arch/arm/boot/dts/tegra30.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)