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[1/6] ARM: dts: imx27: Add SAHARA2 devicetree node

Message ID 1371970490-10874-1-git-send-email-eagle.alexander923@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Alexander Shiyan June 23, 2013, 6:54 a.m. UTC
From: Alexander Shiyan <shc_work@mail.ru>

This patch adds the missing (Symmetric/Asymmetric Hashing and Random
Accelerator) SAHARA2 devicetree node for i.MX27 CPUs.

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 arch/arm/boot/dts/imx27.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Sascha Hauer June 23, 2013, 7:04 p.m. UTC | #1
On Sun, Jun 23, 2013 at 10:54:45AM +0400, Alexander Shiyan wrote:
> From: Alexander Shiyan <shc_work@mail.ru>
> 
> This patch adds the missing (Symmetric/Asymmetric Hashing and Random
> Accelerator) SAHARA2 devicetree node for i.MX27 CPUs.
> 
> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> ---
>  arch/arm/boot/dts/imx27.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> index 0695264..04f9154 100644
> --- a/arch/arm/boot/dts/imx27.dtsi
> +++ b/arch/arm/boot/dts/imx27.dtsi
> @@ -351,6 +351,14 @@
>  				iram = <&iram>;
>  			};
>  
> +			sahara2: sahara@10025000 {
> +				compatible = "fsl,imx27-sahara";
> +				reg = <0x10025000 0x0800>;

I think we should use the whole register space here which would be
0x1000.

Sascha
Sascha Hauer June 23, 2013, 7:06 p.m. UTC | #2
On Sun, Jun 23, 2013 at 10:54:45AM +0400, Alexander Shiyan wrote:
> From: Alexander Shiyan <shc_work@mail.ru>
> 
> This patch adds the missing (Symmetric/Asymmetric Hashing and Random
> Accelerator) SAHARA2 devicetree node for i.MX27 CPUs.
> 
> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>

Apart from the one minor comment:

Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Shawn Guo June 24, 2013, 7:44 a.m. UTC | #3
On Sun, Jun 23, 2013 at 09:04:48PM +0200, Sascha Hauer wrote:
> On Sun, Jun 23, 2013 at 10:54:45AM +0400, Alexander Shiyan wrote:
> > From: Alexander Shiyan <shc_work@mail.ru>
> > 
> > This patch adds the missing (Symmetric/Asymmetric Hashing and Random
> > Accelerator) SAHARA2 devicetree node for i.MX27 CPUs.
> > 
> > Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> > ---
> >  arch/arm/boot/dts/imx27.dtsi | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
> > index 0695264..04f9154 100644
> > --- a/arch/arm/boot/dts/imx27.dtsi
> > +++ b/arch/arm/boot/dts/imx27.dtsi
> > @@ -351,6 +351,14 @@
> >  				iram = <&iram>;
> >  			};
> >  
> > +			sahara2: sahara@10025000 {
> > +				compatible = "fsl,imx27-sahara";
> > +				reg = <0x10025000 0x0800>;
> 
> I think we should use the whole register space here which would be
> 0x1000.

I just fixed it up and applied the series.

Shawn
diff mbox

Patch

diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 0695264..04f9154 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -351,6 +351,14 @@ 
 				iram = <&iram>;
 			};
 
+			sahara2: sahara@10025000 {
+				compatible = "fsl,imx27-sahara";
+				reg = <0x10025000 0x0800>;
+				interrupts = <59>;
+				clocks = <&clks 32>, <&clks 64>;
+				clock-names = "ipg", "ahb";
+			};
+
 			clks: ccm@10027000{
 				compatible = "fsl,imx27-ccm";
 				reg = <0x10027000 0x1000>;