diff mbox

parisc: fix LMMIO mismatch between PAT length and MASK register

Message ID 20130614071142.GB10443@p100.box (mailing list archive)
State Superseded
Headers show

Commit Message

Helge Deller June 14, 2013, 7:11 a.m. UTC
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

The LMMIO length reported by PAT and the length given by the LBA MASK
register are not consistent. This leads e.g. to a non-working ATI FireGL
card with the radeon DRM driver since the memory can't be mapped.

Fix this by correctly adjusting the resource sizes.

Signed-off-by: Helge Deller <deller@gmx.de>

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Comments

Matt Turner June 14, 2013, 7:28 a.m. UTC | #1
On Fri, Jun 14, 2013 at 12:11 AM, Helge Deller <deller@gmx.de> wrote:
> From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
>
> The LMMIO length reported by PAT and the length given by the LBA MASK
> register are not consistent. This leads e.g. to a non-working ATI FireGL
> card with the radeon DRM driver since the memory can't be mapped.
>
> Fix this by correctly adjusting the resource sizes.
>
> Signed-off-by: Helge Deller <deller@gmx.de>
>
> diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
> index 1f05913..7dc0e40 100644
> --- a/drivers/parisc/lba_pci.c
> +++ b/drivers/parisc/lba_pci.c
> @@ -994,6 +994,15 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
>                 case PAT_LMMIO:
>                         /* used to fix up pre-initialized MEM BARs */
>                         if (!lba_dev->hba.lmmio_space.flags) {
> +                               unsigned long lba_len;
> +                               lba_len = ~READ_REG32(lba_dev->hba.base_addr
> +                                               + LBA_LMMIO_MASK);
> +                               if ((p->end - p->start) != lba_len) {
> +                                       pr_warn("PCI%02x LMMIO mismatch between PAT length (0x%lx) and MASK register (0x%lx), fixing.\n",
> +                                         (int)lba_dev->hba.bus_num.start,
> +                                               p->end - p->start, lba_len);
> +                                       p->end = p->start + lba_len;
> +                               }
>                                 sprintf(lba_dev->hba.lmmio_name,
>                                                 "PCI%02x LMMIO",
>                                                 (int)lba_dev->hba.bus_num.start);
> --

With these two patches, does kernel modesetting (and X11?) work?
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Helge Deller June 14, 2013, 7:38 a.m. UTC | #2
* Matt Turner <mattst88@gmail.com>:
> On Fri, Jun 14, 2013 at 12:11 AM, Helge Deller <deller@gmx.de> wrote:
> > From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> >
> > The LMMIO length reported by PAT and the length given by the LBA MASK
> > register are not consistent. This leads e.g. to a non-working ATI FireGL
> > card with the radeon DRM driver since the memory can't be mapped.
> >
> > Fix this by correctly adjusting the resource sizes.
> >
> > Signed-off-by: Helge Deller <deller@gmx.de>
> >
> > diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
> > index 1f05913..7dc0e40 100644
> > --- a/drivers/parisc/lba_pci.c
> > +++ b/drivers/parisc/lba_pci.c
> > @@ -994,6 +994,15 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
> >                 case PAT_LMMIO:
> >                         /* used to fix up pre-initialized MEM BARs */
> >                         if (!lba_dev->hba.lmmio_space.flags) {
> > +                               unsigned long lba_len;
> > +                               lba_len = ~READ_REG32(lba_dev->hba.base_addr
> > +                                               + LBA_LMMIO_MASK);
> > +                               if ((p->end - p->start) != lba_len) {
> > +                                       pr_warn("PCI%02x LMMIO mismatch between PAT length (0x%lx) and MASK register (0x%lx), fixing.\n",
> > +                                         (int)lba_dev->hba.bus_num.start,
> > +                                               p->end - p->start, lba_len);
> > +                                       p->end = p->start + lba_len;
> > +                               }
> >                                 sprintf(lba_dev->hba.lmmio_name,
> >                                                 "PCI%02x LMMIO",
> >                                                 (int)lba_dev->hba.bus_num.start);
> > --
> 
> With these two patches, does kernel modesetting (and X11?) work?

Yes, C8000 with ATI FireGL works then for me with framebuffer, SMP, serial port...everything I tested so far.

Important: *Disable* RADEON Framebuffer driver, and enable Radeon DRM driver instead!

I did not tested X11 yet (still need to fully install the C8000 with our
unstable) - but Thomas mentioned once that this is needed for X11.

BTW, I'll prepare a new installation CD for all machines soon...hopefully until end of
next week and hopefully when kernel 3.10 is released.

If you want to test, pull from git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git
a)  my "for-3.10" branch, then
b)  my "important-for-3.10" branch (two fixed on which I wait for James)...

PS: Does someone has a C800 with 0x77 serial ports? In that case some
small patch to the serial driver is needed to get it detected....

Helge
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Helge Deller June 14, 2013, 7:40 a.m. UTC | #3
* Helge Deller <deller@gmx.de>:
> PS: Does someone has a C800 with 0x77 serial ports? In that case some
> small patch to the serial driver is needed to get it detected....

I meant C8000 of course...
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Thomas Bogendoerfer June 14, 2013, 8:38 a.m. UTC | #4
On Fri, Jun 14, 2013 at 09:38:27AM +0200, Helge Deller wrote:
> I did not tested X11 yet (still need to fully install the C8000 with our
> unstable) - but Thomas mentioned once that this is needed for X11.

the pci mmap thing is a must for X11 to even get the card detected. This
patch is needed for the FireGL X3 cards with 256MB video memory.

Thomas.
Thomas Bogendoerfer June 14, 2013, 8:39 a.m. UTC | #5
On Fri, Jun 14, 2013 at 09:11:42AM +0200, Helge Deller wrote:
> From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> 
> The LMMIO length reported by PAT and the length given by the LBA MASK
> register are not consistent. This leads e.g. to a non-working ATI FireGL
> card with the radeon DRM driver since the memory can't be mapped.
> 
> Fix this by correctly adjusting the resource sizes.
> 
> Signed-off-by: Helge Deller <deller@gmx.de>

add my Acked-By or Signed-off-by, whatever you like.

BTW. thanks for cleaning up the patches.

Thomas.
Alex Ivanov July 9, 2013, 5:34 a.m. UTC | #6
Helge Deller <deller <at> gmx.de> writes:

> I did not tested X11 yet (still need to fully install the C8000 with our
> unstable) - but Thomas mentioned once that this is needed for X11.

I've built from test-3.10 branch of your repo:
Linux version 3.10.0-rc6-64bit-c3000+ (root@parisc) 
(gcc version 4.6.4 (GCC) ) #4 SMP PREEMPT Mon Jul 8 23:16:48 
MSK 2013

I'm using a c8000 with firegl x3. I approve that console works, 
although in an unaccelerated mode. However xorg isn't:
http://pastebin.com/Y1h2BVHB
The system is latest unstable. The xorg is of 1:7.7+3 version.

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John David Anglin July 9, 2013, 3:18 p.m. UTC | #7
On 7/9/2013 1:34 AM, Alex Ivanov wrote:
> I'm using a c8000 with firegl x3. I approve that console works,
> although in an unaccelerated mode. However xorg isn't:
> http://pastebin.com/Y1h2BVHB
> The system is latest unstable. The xorg is of 1:7.7+3 version.
Suggest you hack arch/parisc/kernel/cache.c to disable this
optimization:

         /* Flushing the whole cache on each cpu takes forever on
            rp3440, etc.  So, avoid it if the mm isn't too big.  */
         if (mm_total_size(mm) < parisc_cache_flush_threshold) {

It is probably the get_ptep call in the non current case that's failing
with firegl x3.  It would be useful if you could test if the current case
, "mm->context == mfsp(3)" case works.  You would have to move return
and disable non current block.

Dave
Alex Ivanov July 9, 2013, 7:45 p.m. UTC | #8
John David Anglin <dave.anglin <at> bell.net> writes:

> It would be useful if you could test if the current case
> , "mm->context == mfsp(3)" case works.
> You would have to move return
> and disable non current block.

Done. The system seems to work as usual. Should i do 
some specific checks?

> Suggest you hack arch/parisc/kernel/cache.c to 
> disable this optimization

The panic on SMP kernel changed to another one:
http://pastebin.com/SfUfd0Un
Same was before with an UP kernel. The only thing
i've changed since is moving to the latest toolchains.
Can't reproduce the previous panic case, so can't
comment on your proposed solution.

P.S.: The hw is not faulty, works ok under hpux.

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diff mbox

Patch

diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 1f05913..7dc0e40 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -994,6 +994,15 @@  lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 		case PAT_LMMIO:
 			/* used to fix up pre-initialized MEM BARs */
 			if (!lba_dev->hba.lmmio_space.flags) {
+				unsigned long lba_len;
+				lba_len = ~READ_REG32(lba_dev->hba.base_addr
+						+ LBA_LMMIO_MASK);
+				if ((p->end - p->start) != lba_len) {
+					pr_warn("PCI%02x LMMIO mismatch between PAT length (0x%lx) and MASK register (0x%lx), fixing.\n",
+					  (int)lba_dev->hba.bus_num.start,
+						p->end - p->start, lba_len);
+					p->end = p->start + lba_len;
+				}
 				sprintf(lba_dev->hba.lmmio_name,
 						"PCI%02x LMMIO",
 						(int)lba_dev->hba.bus_num.start);