| Message ID | ea2d30d47cb54b4322231f5c319663ee9c996784.1377202730.git.joshc@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/09/2013 02:37 PM, Josh Cartwright wrote: Patch description? > diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt > +Required properties: > +- compatible : should be "qcom,spmi-pmic-arb". > +- reg-names : should be "core", "intr", "cnfg" > +- reg : offset and length of the PMIC Arbiter Core register map. > +- reg : offset and length of the PMIC Arbiter Interrupt controller register map. > +- reg : offset and length of the PMIC Arbiter Configuration register map. This seems like it's defining the "reg" property 3 times each with a different meaning. It'd be better to say something like: reg : register specifier. Must contain 3 entries, in the following order: core registers, interrupt register, configuration registers. > + qcom,spmi@fc4c0000 { ... > + qcom,pm8841@4 { Node names typically don't include a vendor prefix. For the first instance above, I think just "spmi@fc4c0000" or even just "spmi" would be appropriate here; the latter being best in the case where there's only 1 SPMI controller and hence no need to include the unit address for uniqueness.
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt new file mode 100644 index 0000000..3965236 --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -0,0 +1,36 @@ +Qualcomm SPMI Controller (PMIC Arbiter) + +The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI +controller with wrapping arbitration logic to allow for multiple on-chip +devices to control a single SPMI master. + +See spmi.txt for the generic SPMI controller bindings. + +Required properties: +- compatible : should be "qcom,spmi-pmic-arb". +- reg-names : should be "core", "intr", "cnfg" +- reg : offset and length of the PMIC Arbiter Core register map. +- reg : offset and length of the PMIC Arbiter Interrupt controller register map. +- reg : offset and length of the PMIC Arbiter Configuration register map. +- #address-cells : must be set to 1 +- #size-cells : must be set to 0 + +Child nodes: + +Zero or more child nodes must be specified as per the spmi.txt document. + +Example: + + qcom,spmi@fc4c0000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8841@4 { + reg = <0x4>; + }; + };
Signed-off-by: Josh Cartwright <joshc@codeaurora.org> --- .../bindings/spmi/qcom,spmi-pmic-arb.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt