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[v3,12/15] drm/i915: Band Gap WA

Message ID 397f51dd0b16bf9ca9e5004524a9bbc8532eef46.1377604770.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jani Nikula Aug. 27, 2013, 12:12 p.m. UTC 
From: Shobhit Kumar <shobhit.kumar@intel.com>

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: ymohanma <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   48 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Comments

Lespiau, Damien Aug. 29, 2013, 9:48 a.m. UTC | #1 
On Tue, Aug 27, 2013 at 03:12:24PM +0300, Jani Nikula wrote:
> +static void band_gap_wa(struct drm_i915_private *dev_priv)
> +{
> +	mutex_lock(&dev_priv->dpio_lock);
> +
> +	/* Enable bandgap fix in GOP driver */
> +	vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);

I hear that the new way of doing the band gap reset is through the
flisdsi sideband interface (instead of CCK) to shave off non necessary
delays.

Yogesh, should we upstream the flisdsi version of this patch instead?
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 263c8d2..674fd49 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -37,6 +37,51 @@ 
 static const struct intel_dsi_device intel_dsi_devices[] = {
 };
 
+
+static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val,
+			   u32 mask)
+{
+	u32 tmp = vlv_cck_read(dev_priv, reg);
+	tmp &= ~mask;
+	tmp |= val;
+	vlv_cck_write(dev_priv, reg, tmp);
+}
+
+static void band_gap_wa(struct drm_i915_private *dev_priv)
+{
+	mutex_lock(&dev_priv->dpio_lock);
+
+	/* Enable bandgap fix in GOP driver */
+	vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000);
+	msleep(20);
+	vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000);
+	msleep(20);
+	vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000);
+	msleep(20);
+	vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000);
+	msleep(20);
+	vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000);
+	msleep(20);
+
+	/* Turn Display Trunk on */
+	vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000);
+	msleep(20);
+
+	vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000);
+	msleep(20);
+
+	vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000);
+	msleep(20);
+	vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000);
+	msleep(20);
+	vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000);
+
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	/* Need huge delay, otherwise clock is not stable */
+	msleep(100);
+}
+
 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
 {
 	return container_of(intel_attached_encoder(connector),
@@ -310,6 +355,9 @@  static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 	/* Update the DSI PLL */
 	vlv_enable_dsi_pll(intel_encoder);
 
+	/* XXX: Location of the call */
+	band_gap_wa(dev_priv);
+
 	/* escape clock divider, 20MHz, shared for A and C. device ready must be
 	 * off when doing this! txclkesc? */
 	tmp = I915_READ(MIPI_CTRL(0));