| Message ID | 1377118427-20644-1-git-send-email-dinguyen@altera.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed 2013-08-21 15:53:44, dinguyen@altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > Set the correct clock entries for the the timers, and also clean up > the timer entries for SOCFPGA by removing timer<n> in the timer entry. > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > CC: Rob Herring <rob.herring@calxeda.com> > Cc: Pawel Moll <pawel.moll@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Stephen Warren <swarren@wwwdotorg.org> > Cc: Ian Campbell <ian.campbell@citrix.com> > CC: Arnd Bergmann <arnd@arndb.de> > Cc: Olof Johansson <olof@lixom.net> > CC: Jamie Iles <jamie@jamieiles.com> > Cc: John Stultz <john.stultz@linaro.org> > Cc: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Pavel Machek <pavel@denx.de>
Hi! On Wed, Aug 21, 2013 at 03:53:44PM -0500, dinguyen@altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > Set the correct clock entries for the the timers, and also clean up > the timer entries for SOCFPGA by removing timer<n> in the timer entry. > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > CC: Rob Herring <rob.herring@calxeda.com> > Cc: Pawel Moll <pawel.moll@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Stephen Warren <swarren@wwwdotorg.org> > Cc: Ian Campbell <ian.campbell@citrix.com> > CC: Arnd Bergmann <arnd@arndb.de> > Cc: Olof Johansson <olof@lixom.net> > CC: Jamie Iles <jamie@jamieiles.com> > Cc: John Stultz <john.stultz@linaro.org> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Pavel Machek <pavel@denx.de> > Cc: devicetree@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > --- > arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++-------- > arch/arm/boot/dts/socfpga_cyclone5.dts | 8 ++++---- > arch/arm/boot/dts/socfpga_vt.dts | 8 ++++---- > 3 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > index 9706767..9957bae 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/socfpga.dtsi > @@ -26,10 +26,6 @@ > ethernet1 = &gmac1; > serial0 = &uart0; > serial1 = &uart1; > - timer0 = &timer0; > - timer1 = &timer1; > - timer2 = &timer2; > - timer3 = &timer3; > }; > Yes. Do that. > cpus { > @@ -486,28 +482,32 @@ > interrupts = <1 13 0xf04>; > }; > > - timer0: timer0@ffc08000 { > + timer@ffc08000 { No. Why? Than I can not write something like &timer0 { clock-frequency = <100000000>; }; and would have to reference the whole tree ala / { soc { timer@ffc08000 { clock-frequency = <100000000>; }; }; }; in a boardspecific or SoC specific file (see below). > diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts > index 698dde9..c1af01c 100644 > --- a/arch/arm/boot/dts/socfpga_cyclone5.dts > +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts > > diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts > index 6f23121..72ff14c 100644 > --- a/arch/arm/boot/dts/socfpga_vt.dts > +++ b/arch/arm/boot/dts/socfpga_vt.dts Leads me to a question about terminology: Is the cyclone5 an actual board? AFAIK it is. And the Cyclone 5 FPGA is also called socfpga? Is that correct? But then, seeing that, in an other patch, you add two different sysmgr addresses to the socfpga_vt and socfpga_cyclone5, there are different socfpgas? I want to write a devicetree for the SoCkit. It has a Cyclone 5 on it. So naturally I would now go and include the socfpga_cyclone5.dtsi, with all the cyclone5 stuff and just add my board specific stuff in a socfpga_sockit.dts. But there is no socfpga_cyclone5.dtsi, just the socfpga_cyclone5.dts, which itself seems to be a board... So, how should we reorder the current dts (as I tested with current mainline, the support is completely broken out of the box, but works fine with your patches that are floating around, there should be no users as of now)? Something like: socfpga.dtsi -> socfpga_cyclone5.dtsi --> socfpga_cyclone5_devboard.dts (?) --> socfpga_sockit.dts -> socfpga_???.dtsi --> socfpga_vt.dts ? Thanks and regards, Steffen
Hi Steffen, On Wed, 2013-08-28 at 17:31 +0200, Steffen Trumtrar wrote: > Hi! > > On Wed, Aug 21, 2013 at 03:53:44PM -0500, dinguyen@altera.com wrote: > > From: Dinh Nguyen <dinguyen@altera.com> > > > > Set the correct clock entries for the the timers, and also clean up > > the timer entries for SOCFPGA by removing timer<n> in the timer entry. > > > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > > CC: Rob Herring <rob.herring@calxeda.com> > > Cc: Pawel Moll <pawel.moll@arm.com> > > Cc: Mark Rutland <mark.rutland@arm.com> > > Cc: Stephen Warren <swarren@wwwdotorg.org> > > Cc: Ian Campbell <ian.campbell@citrix.com> > > CC: Arnd Bergmann <arnd@arndb.de> > > Cc: Olof Johansson <olof@lixom.net> > > CC: Jamie Iles <jamie@jamieiles.com> > > Cc: John Stultz <john.stultz@linaro.org> > > Cc: Heiko Stuebner <heiko@sntech.de> > > Cc: Pavel Machek <pavel@denx.de> > > Cc: devicetree@vger.kernel.org > > Cc: linux-arm-kernel@lists.infradead.org > > --- > > arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++-------- > > arch/arm/boot/dts/socfpga_cyclone5.dts | 8 ++++---- > > arch/arm/boot/dts/socfpga_vt.dts | 8 ++++---- > > 3 files changed, 16 insertions(+), 16 deletions(-) > > > > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > > index 9706767..9957bae 100644 > > --- a/arch/arm/boot/dts/socfpga.dtsi > > +++ b/arch/arm/boot/dts/socfpga.dtsi > > @@ -26,10 +26,6 @@ > > ethernet1 = &gmac1; > > serial0 = &uart0; > > serial1 = &uart1; > > - timer0 = &timer0; > > - timer1 = &timer1; > > - timer2 = &timer2; > > - timer3 = &timer3; > > }; > > > > Yes. Do that. > > > cpus { > > @@ -486,28 +482,32 @@ > > interrupts = <1 13 0xf04>; > > }; > > > > - timer0: timer0@ffc08000 { > > + timer@ffc08000 { > > No. Why? Than I can not write something like > > &timer0 { > clock-frequency = <100000000>; > }; > > and would have to reference the whole tree ala > > / { > soc { > timer@ffc08000 { > clock-frequency = <100000000>; > }; > }; > }; > > in a boardspecific or SoC specific file (see below). Agreed. Will adjust accordingly. > > > diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts > > index 698dde9..c1af01c 100644 > > --- a/arch/arm/boot/dts/socfpga_cyclone5.dts > > +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts > > > > diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts > > index 6f23121..72ff14c 100644 > > --- a/arch/arm/boot/dts/socfpga_vt.dts > > +++ b/arch/arm/boot/dts/socfpga_vt.dts > > Leads me to a question about terminology: Is the cyclone5 an actual board? > AFAIK it is. And the Cyclone 5 FPGA is also called socfpga? Is that correct? > But then, seeing that, in an other patch, you add two different sysmgr addresses to > the socfpga_vt and socfpga_cyclone5, there are different socfpgas? Yes, sofpga_cyclone5.dts is the devkit that is manufactured by Altera. socfpga_vt.dts is a virtual platform for SOCFPGA. You can get the virtual platform from Synopsis. It mimics everything except the FPGA. socfpga is the base SOC with a Cyclone 5 FPGA on it. I'll be upstreaming socfpga_arria5 soon, which has the SOCFPGA + Arria 5 FPGA. > > I want to write a devicetree for the SoCkit. It has a Cyclone 5 on it. > So naturally I would now go and include the socfpga_cyclone5.dtsi, with all the > cyclone5 stuff and just add my board specific stuff in a socfpga_sockit.dts. > But there is no socfpga_cyclone5.dtsi, just the socfpga_cyclone5.dts, which itself > seems to be a board... socfpga.dtsi is the base DTSI for the platform. In hindsight, I should have named it a bit different, but for now socfpga_cyclone5 is for the board. > > So, how should we reorder the current dts (as I tested with current mainline, the > support is completely broken out of the box, but works fine with your patches that > are floating around, there should be no users as of now)? Not sure what you mean by broken. I was able to boot 3.11-rc7 just now using an initramfs. As you can already tell, I'm doing my best to get more support for the platform upstream, but it will take time. In the meantim, you get our latest downstream kernel at: git://git.rocketboards.org/linux-socfpga.git Dinh > > Something like: > > socfpga.dtsi > -> socfpga_cyclone5.dtsi > --> socfpga_cyclone5_devboard.dts (?) > --> socfpga_sockit.dts > -> socfpga_???.dtsi > --> socfpga_vt.dts > > ? > > Thanks and regards, > Steffen >
Hi Dinh, On Thu, Aug 29, 2013 at 10:55:18AM -0500, Dinh Nguyen wrote: > Hi Steffen, > > > @@ -486,28 +482,32 @@ > > > interrupts = <1 13 0xf04>; > > > }; > > > > > > - timer0: timer0@ffc08000 { > > > + timer@ffc08000 { > > > > No. Why? Than I can not write something like > > > > &timer0 { > > clock-frequency = <100000000>; > > }; > > > > and would have to reference the whole tree ala > > > > / { > > soc { > > timer@ffc08000 { > > clock-frequency = <100000000>; > > }; > > }; > > }; > > > > in a boardspecific or SoC specific file (see below). > > Agreed. Will adjust accordingly. > Good. > > > > > diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts > > > index 698dde9..c1af01c 100644 > > > --- a/arch/arm/boot/dts/socfpga_cyclone5.dts > > > +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts > > > > > > diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts > > > index 6f23121..72ff14c 100644 > > > --- a/arch/arm/boot/dts/socfpga_vt.dts > > > +++ b/arch/arm/boot/dts/socfpga_vt.dts > > > > Leads me to a question about terminology: Is the cyclone5 an actual board? > > AFAIK it is. And the Cyclone 5 FPGA is also called socfpga? Is that correct? > > But then, seeing that, in an other patch, you add two different sysmgr addresses to > > the socfpga_vt and socfpga_cyclone5, there are different socfpgas? > > Yes, sofpga_cyclone5.dts is the devkit that is manufactured by Altera. > socfpga_vt.dts is a virtual platform for SOCFPGA. You can get the > virtual platform from Synopsis. It mimics everything except the FPGA. > Uh, nice. I will check out the vt. > socfpga is the base SOC with a Cyclone 5 FPGA on it. I'll be upstreaming > socfpga_arria5 soon, which has the SOCFPGA + Arria 5 FPGA. > Hm, okay. That might lead to confusion then... > > > > I want to write a devicetree for the SoCkit. It has a Cyclone 5 on it. > > So naturally I would now go and include the socfpga_cyclone5.dtsi, with all the > > cyclone5 stuff and just add my board specific stuff in a socfpga_sockit.dts. > > But there is no socfpga_cyclone5.dtsi, just the socfpga_cyclone5.dts, which itself > > seems to be a board... > > socfpga.dtsi is the base DTSI for the platform. In hindsight, I should > have named it a bit different, but for now socfpga_cyclone5 is for the > board. > and we should make the socfpga_cyclone5 a dtsi. I can do that. It's early in development and I see no reason not to fix it now. We have seen quite a lot of rearrangment with the imx6 for example. No need to duplicate it, if we know it beforehand. > > > > So, how should we reorder the current dts (as I tested with current mainline, the > > support is completely broken out of the box, but works fine with your patches that > > are floating around, there should be no users as of now)? > > Not sure what you mean by broken. I was able to boot 3.11-rc7 just now > using an initramfs. As you can already tell, I'm doing my best to get > more support for the platform upstream, but it will take time. > Yeah, broken might have been a bit harsh :-D But my first experience with the mainline kernel was a scrambled serial console and hanging system as soon as you use the ethernet/ip=dhcp. And the SD wasn't working for me, too. But those SD cards are really more problematic than one might think, so... But as I said: with your patch series, both is working. Looking forward to your next versions of those patches. Now I have a hanging system, when I add the at24 on i2c-0, what ever might be the reason for that :-D BTW: you don't happen to have any insight in what crazy things you do with the CRC32 in your prebootloader, do you? Been trying some time to calculate the crc, but never got to the one the mkpimage generates. It doesn't seem to be what crc32 or chksum calculate or the datasheet is missing some essential info for me to understand it. Regards, Steffen
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 9706767..9957bae 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -26,10 +26,6 @@ ethernet1 = &gmac1; serial0 = &uart0; serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; }; cpus { @@ -486,28 +482,32 @@ interrupts = <1 13 0xf04>; }; - timer0: timer0@ffc08000 { + timer@ffc08000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; + clocks = <&osc>; }; - timer1: timer1@ffc09000 { + timer@ffc09000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; + clocks = <&osc>; }; - timer2: timer2@ffd00000 { + timer@ffd00000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; + clocks = <&l4_sp_clk>; }; - timer3: timer3@ffd01000 { + timer@ffd01000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; + clocks = <&l4_sp_clk>; }; uart0: serial0@ffc02000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 698dde9..c1af01c 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -67,19 +67,19 @@ }; }; - timer0@ffc08000 { + timer@ffc08000 { clock-frequency = <100000000>; }; - timer1@ffc09000 { + timer@ffc09000 { clock-frequency = <100000000>; }; - timer2@ffd00000 { + timer@ffd00000 { clock-frequency = <25000000>; }; - timer3@ffd01000 { + timer@ffd01000 { clock-frequency = <25000000>; }; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 6f23121..72ff14c 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -57,19 +57,19 @@ }; }; - timer0@ffc08000 { + timer@ffc08000 { clock-frequency = <7000000>; }; - timer1@ffc09000 { + timer@ffc09000 { clock-frequency = <7000000>; }; - timer2@ffd00000 { + timer@ffd00000 { clock-frequency = <7000000>; }; - timer3@ffd01000 { + timer@ffd01000 { clock-frequency = <7000000>; };