| Message ID | 1376243970-6489-10-git-send-email-tomasz.figa@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Sun, Aug 11, 2013 at 7:59 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote: > The legacy S3C-DMA API required every period of a cyclic buffer to be > queued separately. After conversion of Samsung ASoC to Samsung DMA > wrappers somebody made an assumption that the same is needed for DMA > engine API, which is not true. > > In effect, Samsung ASoC DMA code was queuing the whole cyclic buffer > multiple times with a shift of one period per iteration, leading to: > a) severe memory waste - up to 13x times more DMA transfer descriptors > are allocated than needed, > b) possible memory corruption, because further cyclic buffers were out > of the original buffers, due to the offset. > > This patch fixes this problem by making the legacy S3C-DMA API use the > same semantics as DMA engine (the whole cyclic buffer is enqueued at > once) and modifying users of Samsung DMA wrappers in cyclic mode to > behave appropriately. > > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> > Acked-by: Linus Walleij <linus.walleij@linaro.org> If patch 1 thru 9 are uncontroversial now, maybe Vinod can apply these for v3.12 so we can get less noise and risk of collissions in the next merge window? Just an idea. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wednesday 28 of August 2013 09:06:27 Linus Walleij wrote: > On Sun, Aug 11, 2013 at 7:59 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote: > > The legacy S3C-DMA API required every period of a cyclic buffer to be > > queued separately. After conversion of Samsung ASoC to Samsung DMA > > wrappers somebody made an assumption that the same is needed for DMA > > engine API, which is not true. > > > > In effect, Samsung ASoC DMA code was queuing the whole cyclic buffer > > > > multiple times with a shift of one period per iteration, leading to: > > a) severe memory waste - up to 13x times more DMA transfer > > descriptors > > > > are allocated than needed, > > > > b) possible memory corruption, because further cyclic buffers were > > out > > > > of the original buffers, due to the offset. > > > > This patch fixes this problem by making the legacy S3C-DMA API use the > > same semantics as DMA engine (the whole cyclic buffer is enqueued at > > once) and modifying users of Samsung DMA wrappers in cyclic mode to > > behave appropriately. > > > > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > If patch 1 thru 9 are uncontroversial now, maybe Vinod can apply > these for v3.12 so we can get less noise and risk of collissions > in the next merge window? > > Just an idea. That would be nice, leaving only Samsung-specific patches for the next merge window. (That would be patches 1 to 8, though, as 9 is a patch for ASoC that could be picked up by Mark Brown independently.) Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Aug 28, 2013 at 09:06:27AM +0200, Linus Walleij wrote: > If patch 1 thru 9 are uncontroversial now, maybe Vinod can apply > these for v3.12 so we can get less noise and risk of collissions > in the next merge window? Patch 9 I was going to apply to ASoC towards the end of the release cycle - it shouldn't depend on the earlier ones as ASoC isn't using dmaengine yet. Holding off partly to run testing and partly in case this ends up getting applied.
On Sun, Aug 11, 2013 at 07:59:21PM +0200, Tomasz Figa wrote: > The legacy S3C-DMA API required every period of a cyclic buffer to be > queued separately. After conversion of Samsung ASoC to Samsung DMA > wrappers somebody made an assumption that the same is needed for DMA > engine API, which is not true. Applied, thanks.
On Thu, Aug 29, 2013 at 6:36 PM, Mark Brown <broonie@kernel.org> wrote: > On Sun, Aug 11, 2013 at 07:59:21PM +0200, Tomasz Figa wrote: >> The legacy S3C-DMA API required every period of a cyclic buffer to be >> queued separately. After conversion of Samsung ASoC to Samsung DMA >> wrappers somebody made an assumption that the same is needed for DMA >> engine API, which is not true. > > Applied, thanks. OK Vinod can you take in patch 1 thru 8? Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c index 0cc40ae..98b10ba 100644 --- a/arch/arm/plat-samsung/s3c-dma-ops.c +++ b/arch/arm/plat-samsung/s3c-dma-ops.c @@ -82,7 +82,8 @@ static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param) static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param) { struct cb_data *data; - int len = (param->cap == DMA_CYCLIC) ? param->period : param->len; + dma_addr_t pos = param->buf; + dma_addr_t end = param->buf + param->len; list_for_each_entry(data, &dma_list, node) if (data->ch == ch) @@ -94,7 +95,15 @@ static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param) data->fp_param = param->fp_param; } - s3c2410_dma_enqueue(ch, (void *)data, param->buf, len); + if (param->cap != DMA_CYCLIC) { + s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len); + return 0; + } + + while (pos < end) { + s3c2410_dma_enqueue(ch, (void *)data, pos, param->period); + pos += param->period; + } return 0; } diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c index 21b7926..6e2b2b4 100644 --- a/sound/soc/samsung/dma.c +++ b/sound/soc/samsung/dma.c @@ -90,6 +90,13 @@ static void dma_enqueue(struct snd_pcm_substream *substream) dma_info.period = prtd->dma_period; dma_info.len = prtd->dma_period*limit; + if (dma_info.cap == DMA_CYCLIC) { + dma_info.buf = pos; + prtd->params->ops->prepare(prtd->params->ch, &dma_info); + prtd->dma_loaded += limit; + return; + } + while (prtd->dma_loaded < limit) { pr_debug("dma_loaded: %d\n", prtd->dma_loaded);
The legacy S3C-DMA API required every period of a cyclic buffer to be queued separately. After conversion of Samsung ASoC to Samsung DMA wrappers somebody made an assumption that the same is needed for DMA engine API, which is not true. In effect, Samsung ASoC DMA code was queuing the whole cyclic buffer multiple times with a shift of one period per iteration, leading to: a) severe memory waste - up to 13x times more DMA transfer descriptors are allocated than needed, b) possible memory corruption, because further cyclic buffers were out of the original buffers, due to the offset. This patch fixes this problem by making the legacy S3C-DMA API use the same semantics as DMA engine (the whole cyclic buffer is enqueued at once) and modifying users of Samsung DMA wrappers in cyclic mode to behave appropriately. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> --- arch/arm/plat-samsung/s3c-dma-ops.c | 13 +++++++++++-- sound/soc/samsung/dma.c | 7 +++++++ 2 files changed, 18 insertions(+), 2 deletions(-)