| Message ID | 1380152133-1024-1-git-send-email-benjamin.widawsky@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Sep 25, 2013 at 04:35:32PM -0700, Ben Widawsky wrote: > This allows us to keep track of the values being set if we want to tweak > this code. > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > --- > drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d27eda6..31cf188 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3671,6 +3671,9 @@ void gen6_update_ring_freq(struct drm_device *dev) > ring_freq = (gpu_freq * 5 + 3) / 4; > ring_freq = max(min_ring_freq, ring_freq); > /* leave ia_freq as the default, chosen by cpufreq */ > + > + DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n", > + ring_freq * 100, gpu_freq * 50); > } else { > /* On older processors, there is no separate ring > * clock domain, so in order to boost the bandwidth > @@ -3684,6 +3687,9 @@ void gen6_update_ring_freq(struct drm_device *dev) > else > ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); > ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); > + > + DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n", > + ia_freq * 100, gpu_freq * 50); This is not a ring freq, but a cpu core freq. Also would be wise to point out that this information is in /sys/kernel/debug/dri/0/i915_ring_freq_table -Chris
On Thu, Sep 26, 2013 at 12:49:37AM +0100, Chris Wilson wrote: > On Wed, Sep 25, 2013 at 04:35:32PM -0700, Ben Widawsky wrote: > > This allows us to keep track of the values being set if we want to tweak > > this code. > > > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > > --- > > drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index d27eda6..31cf188 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3671,6 +3671,9 @@ void gen6_update_ring_freq(struct drm_device *dev) > > ring_freq = (gpu_freq * 5 + 3) / 4; > > ring_freq = max(min_ring_freq, ring_freq); > > /* leave ia_freq as the default, chosen by cpufreq */ > > + > > + DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n", > > + ring_freq * 100, gpu_freq * 50); > > } else { > > /* On older processors, there is no separate ring > > * clock domain, so in order to boost the bandwidth > > @@ -3684,6 +3687,9 @@ void gen6_update_ring_freq(struct drm_device *dev) > > else > > ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); > > ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); > > + > > + DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n", > > + ia_freq * 100, gpu_freq * 50); > > This is not a ring freq, but a cpu core freq. > Also would be wise to point out that this information is in > /sys/kernel/debug/dri/0/i915_ring_freq_table > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre Ooops. I forgot about that interface. Ignore this patch. You are incorrect in saying it's _just_ the CPU core frequency. This is the ring and IA frequency on SNB + IVB. The frequency is tied to the CPU core on SNB + IVB. It is not tied to the cpu core on Haswell. To make the print more generic, and correct across the board it makes sense to say we're setting the ring frequency (to me). Even the programming guides typically call this, "IA/ring" frequency. Above is only for posterity. Again, forget the patch.
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d27eda6..31cf188 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3671,6 +3671,9 @@ void gen6_update_ring_freq(struct drm_device *dev) ring_freq = (gpu_freq * 5 + 3) / 4; ring_freq = max(min_ring_freq, ring_freq); /* leave ia_freq as the default, chosen by cpufreq */ + + DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n", + ring_freq * 100, gpu_freq * 50); } else { /* On older processors, there is no separate ring * clock domain, so in order to boost the bandwidth @@ -3684,6 +3687,9 @@ void gen6_update_ring_freq(struct drm_device *dev) else ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); + + DRM_DEBUG_DRIVER("Setup min ring frequency %dMHz for GT freq %dMHz\n", + ia_freq * 100, gpu_freq * 50); } sandybridge_pcode_write(dev_priv,
This allows us to keep track of the values being set if we want to tweak this code. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ 1 file changed, 6 insertions(+)