| Message ID | 1381324359-28825-1-git-send-email-tomi.valkeinen@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/09/2013 04:12 PM, Tomi Valkeinen wrote: > Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can > be configured without the need to get the parent of the fclk. I wouldn't touch this file right now, as we are trying to move the clock data over to DT. Legacy boot support probably requires to do this update, but I would rather wait a bit and do the modifications to both DT clock data and this file in the same patch. Same applies for other patches also. -Tero > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > --- > arch/arm/mach-omap2/cclock44xx_data.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c > index b237950..ec0dc0b 100644 > --- a/arch/arm/mach-omap2/cclock44xx_data.c > +++ b/arch/arm/mach-omap2/cclock44xx_data.c > @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, > OMAP4430_CM_DSS_DSS_CLKCTRL, > OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); > > -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, > +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, > + CLK_SET_RATE_PARENT, > OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, > 0x0, NULL); > >
On 09/10/13 16:22, Tero Kristo wrote: > On 10/09/2013 04:12 PM, Tomi Valkeinen wrote: >> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can >> be configured without the need to get the parent of the fclk. > > I wouldn't touch this file right now, as we are trying to move the clock > data over to DT. Legacy boot support probably requires to do this > update, but I would rather wait a bit and do the modifications to both > DT clock data and this file in the same patch. Same applies for other > patches also. Sounds good. I don't have any particular wishes how this is done, but I'd really like these to go into 3.13. The fclk handling in omapdss is quite a mess, and these flags would make it possible to clean it up. And the reason it's important to clean up the fclk handling ASAP is AM43xx, which has yet another clocking scheme. If these get only to 3.14, then I can fix the fclk handling only on 3.15. Tomi
Hi Tony, Tero, On 09/10/13 16:12, Tomi Valkeinen wrote: > Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can > be configured without the need to get the parent of the fclk. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > --- > arch/arm/mach-omap2/cclock44xx_data.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c > index b237950..ec0dc0b 100644 > --- a/arch/arm/mach-omap2/cclock44xx_data.c > +++ b/arch/arm/mach-omap2/cclock44xx_data.c > @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, > OMAP4430_CM_DSS_DSS_CLKCTRL, > OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); > > -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, > +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, > + CLK_SET_RATE_PARENT, > OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, > 0x0, NULL); I was discussing with Tero about these three patches, and he was ok with them being merged. Tony, it'd be great to have these for 3.13, so that I can start cleaning up the DSS driver's fclk management. Tomi
On 10/24/2013 11:03 AM, Tomi Valkeinen wrote: > Hi Tony, Tero, > > On 09/10/13 16:12, Tomi Valkeinen wrote: >> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can >> be configured without the need to get the parent of the fclk. >> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> >> --- >> arch/arm/mach-omap2/cclock44xx_data.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c >> index b237950..ec0dc0b 100644 >> --- a/arch/arm/mach-omap2/cclock44xx_data.c >> +++ b/arch/arm/mach-omap2/cclock44xx_data.c >> @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, >> OMAP4430_CM_DSS_DSS_CLKCTRL, >> OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); >> >> -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, >> +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, >> + CLK_SET_RATE_PARENT, >> OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, >> 0x0, NULL); > > I was discussing with Tero about these three patches, and he was ok with > them being merged. > > Tony, it'd be great to have these for 3.13, so that I can start cleaning > up the DSS driver's fclk management. Yea, am ok with these, I can incorporate the changes to my DT clk series. -Tero
* Tero Kristo <t-kristo@ti.com> [131024 06:23]: > On 10/24/2013 11:03 AM, Tomi Valkeinen wrote: > >Hi Tony, Tero, > > > >On 09/10/13 16:12, Tomi Valkeinen wrote: > >>Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can > >>be configured without the need to get the parent of the fclk. > >> > >>Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > >>--- > >> arch/arm/mach-omap2/cclock44xx_data.c | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >>diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c > >>index b237950..ec0dc0b 100644 > >>--- a/arch/arm/mach-omap2/cclock44xx_data.c > >>+++ b/arch/arm/mach-omap2/cclock44xx_data.c > >>@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, > >> OMAP4430_CM_DSS_DSS_CLKCTRL, > >> OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); > >> > >>-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, > >>+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, > >>+ CLK_SET_RATE_PARENT, > >> OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, > >> 0x0, NULL); > > > >I was discussing with Tero about these three patches, and he was ok with > >them being merged. > > > >Tony, it'd be great to have these for 3.13, so that I can start cleaning > >up the DSS driver's fclk management. > > Yea, am ok with these, I can incorporate the changes to my DT clk series. OK. If you have fixes that should go in earlier, please put those into a separate branch. Regards, Tony
On 10/24/2013 04:28 PM, Tony Lindgren wrote: > * Tero Kristo <t-kristo@ti.com> [131024 06:23]: >> On 10/24/2013 11:03 AM, Tomi Valkeinen wrote: >>> Hi Tony, Tero, >>> >>> On 09/10/13 16:12, Tomi Valkeinen wrote: >>>> Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can >>>> be configured without the need to get the parent of the fclk. >>>> >>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> >>>> --- >>>> arch/arm/mach-omap2/cclock44xx_data.c | 3 ++- >>>> 1 file changed, 2 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c >>>> index b237950..ec0dc0b 100644 >>>> --- a/arch/arm/mach-omap2/cclock44xx_data.c >>>> +++ b/arch/arm/mach-omap2/cclock44xx_data.c >>>> @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, >>>> OMAP4430_CM_DSS_DSS_CLKCTRL, >>>> OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); >>>> >>>> -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, >>>> +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, >>>> + CLK_SET_RATE_PARENT, >>>> OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, >>>> 0x0, NULL); >>> >>> I was discussing with Tero about these three patches, and he was ok with >>> them being merged. >>> >>> Tony, it'd be great to have these for 3.13, so that I can start cleaning >>> up the DSS driver's fclk management. >> >> Yea, am ok with these, I can incorporate the changes to my DT clk series. > > OK. If you have fixes that should go in earlier, please put those into > a separate branch. This is for Paul I guess, I meant I will do the changes needed for the DT series to get same fixes there. -Tero
* Tero Kristo <t-kristo@ti.com> [131024 06:32]: > On 10/24/2013 04:28 PM, Tony Lindgren wrote: > >* Tero Kristo <t-kristo@ti.com> [131024 06:23]: > >>On 10/24/2013 11:03 AM, Tomi Valkeinen wrote: > >>>Hi Tony, Tero, > >>> > >>>On 09/10/13 16:12, Tomi Valkeinen wrote: > >>>>Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can > >>>>be configured without the need to get the parent of the fclk. > >>>> > >>>>Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > >>>>--- > >>>> arch/arm/mach-omap2/cclock44xx_data.c | 3 ++- > >>>> 1 file changed, 2 insertions(+), 1 deletion(-) > >>>> > >>>>diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c > >>>>index b237950..ec0dc0b 100644 > >>>>--- a/arch/arm/mach-omap2/cclock44xx_data.c > >>>>+++ b/arch/arm/mach-omap2/cclock44xx_data.c > >>>>@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, > >>>> OMAP4430_CM_DSS_DSS_CLKCTRL, > >>>> OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); > >>>> > >>>>-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, > >>>>+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, > >>>>+ CLK_SET_RATE_PARENT, > >>>> OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, > >>>> 0x0, NULL); > >>> > >>>I was discussing with Tero about these three patches, and he was ok with > >>>them being merged. > >>> > >>>Tony, it'd be great to have these for 3.13, so that I can start cleaning > >>>up the DSS driver's fclk management. > >> > >>Yea, am ok with these, I can incorporate the changes to my DT clk series. > > > >OK. If you have fixes that should go in earlier, please put those into > >a separate branch. > > This is for Paul I guess, I meant I will do the changes needed for > the DT series to get same fixes there. OK, Paul care to take a look and queue or ack if it looks OK to you? Regards, Tony
On Wed, 9 Oct 2013, Tomi Valkeinen wrote: > Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can > be configured without the need to get the parent of the fclk. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Thanks, queued. - Paul
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index b237950..ec0dc0b 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, +DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, + CLK_SET_RATE_PARENT, OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, 0x0, NULL);
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can be configured without the need to get the parent of the fclk. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> --- arch/arm/mach-omap2/cclock44xx_data.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)