| Message ID | 1383164736-1849-5-git-send-email-sboyd@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: > The Krait L1/L2 error reporting device is made up of two > interrupts, one per-CPU interrupt for the L1 caches and one > interrupt for the L2 cache. > > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Kumar Gala <galak@codeaurora.org> > Cc: <devicetree@vger.kernel.org> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> > --- > Documentation/devicetree/bindings/arm/cpus.txt | 49 ++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt > index f32494d..0f7b27f 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.txt > +++ b/Documentation/devicetree/bindings/arm/cpus.txt > @@ -44,6 +44,8 @@ For the ARM architecture every CPU node must contain the following properties: > "marvell,mohawk" > "marvell,xsc3" > "marvell,xscale" > + "qcom,scorpion" > + "qcom,krait" > > Example: > > @@ -75,3 +77,50 @@ Example: > reg = <0x101>; > }; > }; > + > +If the compatible string contains "qcom,krait" there shall be an interrupts > +property containing the L1/CPU error interrupt number. There shall also be an 'also be a' > +l2-cache node containing the following properties: Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? > + > + - compatible: Shall contain at least "cache" > + - cache-level: Must be 2 > + - interrupts: Shall contain the L2 error interrupt > + > +Example: > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <1 9 0xf04>; > + compatible = "qcom,krait"; > + > + cpu@0 { > + device_type = "cpu"; > + reg = <0>; > + next-level-cache = <&L2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + reg = <1>; > + next-level-cache = <&L2>; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + reg = <2>; > + next-level-cache = <&L2>; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + reg = <3>; > + next-level-cache = <&L2>; > + }; > + > + L2: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + interrupts = <0 2 0x4>; > + }; > + }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > hosted by The Linux Foundation >
On 10/30/13 14:45, Kumar Gala wrote: > On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: > >> @@ -75,3 +77,50 @@ Example: >> reg = <0x101>; >> }; >> }; >> + >> +If the compatible string contains "qcom,krait" there shall be an interrupts >> +property containing the L1/CPU error interrupt number. There shall also be an > 'also be a' ok > >> +l2-cache node containing the following properties: > Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? Yes it is per CPU. That is what the 0xf part of the cpus interrupts property is showing. > >> + >> + - compatible: Shall contain at least "cache" >> + - cache-level: Must be 2 >> + - interrupts: Shall contain the L2 error interrupt >> + >> +Example: >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <1 9 0xf04>; >> + compatible = "qcom,krait"; >>
On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote: > On 10/30/13 14:45, Kumar Gala wrote: >> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: >> >>> @@ -75,3 +77,50 @@ Example: >>> reg = <0x101>; >>> }; >>> }; >>> + >>> +If the compatible string contains "qcom,krait" there shall be an interrupts >>> +property containing the L1/CPU error interrupt number. There shall also be an >> 'also be a' > > ok > >> >>> +l2-cache node containing the following properties: >> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? > > Yes it is per CPU. That is what the 0xf part of the cpus interrupts > property is showing. Than why not have it in each cpu node? >>> >>> + - compatible: Shall contain at least "cache" >>> + - cache-level: Must be 2 >>> + - interrupts: Shall contain the L2 error interrupt >>> + >>> +Example: >>> + >>> + cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <1 9 0xf04>; >>> + compatible = "qcom,krait"; >>> - k
On 10/30/13 14:56, Kumar Gala wrote: > On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote: > >> On 10/30/13 14:45, Kumar Gala wrote: >>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: >>>> +l2-cache node containing the following properties: >>> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? >> Yes it is per CPU. That is what the 0xf part of the cpus interrupts >> property is showing. > Than why not have it in each cpu node? Because that duplicates things unnecessarily? The cpus node can hold things that are common to all CPUs to avoid duplication. If it was a different PPI for each CPU then I would agree that we need to put it in each cpu node.
On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote: > On 10/30/13 14:56, Kumar Gala wrote: >> On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote: >> >>> On 10/30/13 14:45, Kumar Gala wrote: >>>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: >>>>> +l2-cache node containing the following properties: >>>> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? >>> Yes it is per CPU. That is what the 0xf part of the cpus interrupts >>> property is showing. >> Than why not have it in each cpu node? > > Because that duplicates things unnecessarily? The cpus node can hold > things that are common to all CPUs to avoid duplication. If it was a > different PPI for each CPU then I would agree that we need to put it in > each cpu node. Ok, I'll accept that as the binding is specific to Krait (and I assume all SoCs w/Krait wire this up to a common interrupt) - k
On 10/30, Kumar Gala wrote: > > On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote: > > > On 10/30/13 14:56, Kumar Gala wrote: > >> On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote: > >> > >>> On 10/30/13 14:45, Kumar Gala wrote: > >>>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: > >>>>> +l2-cache node containing the following properties: > >>>> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? > >>> Yes it is per CPU. That is what the 0xf part of the cpus interrupts > >>> property is showing. > >> Than why not have it in each cpu node? > > > > Because that duplicates things unnecessarily? The cpus node can hold > > things that are common to all CPUs to avoid duplication. If it was a > > different PPI for each CPU then I would agree that we need to put it in > > each cpu node. > > Ok, I'll accept that as the binding is specific to Krait (and I assume all SoCs w/Krait wire this up to a common interrupt) > Can I take that as an ack? I'll resend with the s/an/a/ fix today.
On Oct 31, 2013, at 12:30 PM, Stephen Boyd wrote: > On 10/30, Kumar Gala wrote: >> >> On Oct 30, 2013, at 4:58 PM, Stephen Boyd wrote: >> >>> On 10/30/13 14:56, Kumar Gala wrote: >>>> On Oct 30, 2013, at 4:48 PM, Stephen Boyd wrote: >>>> >>>>> On 10/30/13 14:45, Kumar Gala wrote: >>>>>> On Oct 30, 2013, at 3:25 PM, Stephen Boyd wrote: >>>>>>> +l2-cache node containing the following properties: >>>>>> Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)? >>>>> Yes it is per CPU. That is what the 0xf part of the cpus interrupts >>>>> property is showing. >>>> Than why not have it in each cpu node? >>> >>> Because that duplicates things unnecessarily? The cpus node can hold >>> things that are common to all CPUs to avoid duplication. If it was a >>> different PPI for each CPU then I would agree that we need to put it in >>> each cpu node. >> >> Ok, I'll accept that as the binding is specific to Krait (and I assume all SoCs w/Krait wire this up to a common interrupt) >> > > Can I take that as an ack? I'll resend with the s/an/a/ fix > today. Yes, you can take that as an ack. - k
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index f32494d..0f7b27f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -44,6 +44,8 @@ For the ARM architecture every CPU node must contain the following properties: "marvell,mohawk" "marvell,xsc3" "marvell,xscale" + "qcom,scorpion" + "qcom,krait" Example: @@ -75,3 +77,50 @@ Example: reg = <0x101>; }; }; + +If the compatible string contains "qcom,krait" there shall be an interrupts +property containing the L1/CPU error interrupt number. There shall also be an +l2-cache node containing the following properties: + + - compatible: Shall contain at least "cache" + - cache-level: Must be 2 + - interrupts: Shall contain the L2 error interrupt + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + };
The Krait L1/L2 error reporting device is made up of two interrupts, one per-CPU interrupt for the L1 caches and one interrupt for the L2 cache. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Kumar Gala <galak@codeaurora.org> Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> --- Documentation/devicetree/bindings/arm/cpus.txt | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+)