@@ -100,6 +100,9 @@
# define DP_I2C_SPEED_1M 0x20
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
+# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
+# define DP_FRAMING_CHANGE_CAP (1 << 1)
+# define DP_DPCD_DISPLAY_CONTROL_CAP (1 << 3) /* eDP 1.2 */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
/* Multiple stream transport */
@@ -291,6 +294,32 @@
# define DP_SET_POWER_D0 0x1
# define DP_SET_POWER_D3 0x2
+#define DP_EDP_REV 0x700 /* eDP 1.2 */
+
+#define DP_EDP_GENERAL_CAPABILITY_REGISTER_1 0x701
+#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAPABILITY_REGISTER 0x702
+#define DP_EDP_GENERAL_CAPABILITY_REGISTER_2 0x703
+
+#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
+#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
+#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
+#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
+#define DP_EDP_PWMGEN_BIT_COUNT 0x724
+#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
+#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
+#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
+#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
+
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
+#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
+
+#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
+#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
+
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
Preparing for the future eDP panels. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- include/drm/drm_dp_helper.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)