| Message ID | 1386197576-3825-5-git-send-email-dinguyen@altera.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wednesday 04 December 2013, dinguyen@altera.com wrote: > + > +* compatible: should be > + - "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA > + specific extensions. > + > +* samsung,dw-mshc-sdr-timing: See exynos-dw-mshc.txt for more information about > + this property. > + > +Example: > + dwmmc0@ff704000 { > + compatible = "altr,socfpga-dw-mshc", "snps,dw-mshc"; > + reg = <0xff704000 0x1000>; > + interrupts = <0 139 4>; > + fifo-depth = <0x400>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&l4_mp_clk>, <&sdmmc_clk>, <&sysmgr_sdr_mmc>; > + clock-names = "biu", "ciu", "sysmgr-sdr-mmc"; You add a "sysmgr-sdr-mmc" clock here without documenting it. I think what you actually mean here is > + clocks = <&l4_mp_clk>, <&sysmgr_sdr_mmc>; > + clock-names = "biu", "ciu"; i.e. the <&sysmgr_sdr_mmc> clock is actually your "ciu". If I understand your code correctly, the dw-mshc has exactly two clock inputs, biu and ciu, and you use sysmgr to provide ciu. The driver code already contains logic to set the rate of the ciu clock, and you just need to hook into that. Arnd
On Thu, 2013-12-05 at 04:07 +0100, Arnd Bergmann wrote: > On Wednesday 04 December 2013, dinguyen@altera.com wrote: > > > + > > +* compatible: should be > > + - "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA > > + specific extensions. > > + > > +* samsung,dw-mshc-sdr-timing: See exynos-dw-mshc.txt for more information about > > + this property. > > + > > +Example: > > + dwmmc0@ff704000 { > > + compatible = "altr,socfpga-dw-mshc", "snps,dw-mshc"; > > + reg = <0xff704000 0x1000>; > > + interrupts = <0 139 4>; > > + fifo-depth = <0x400>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&l4_mp_clk>, <&sdmmc_clk>, <&sysmgr_sdr_mmc>; > > + clock-names = "biu", "ciu", "sysmgr-sdr-mmc"; > > You add a "sysmgr-sdr-mmc" clock here without documenting it. I think what you > actually mean here is > > > + clocks = <&l4_mp_clk>, <&sysmgr_sdr_mmc>; > > + clock-names = "biu", "ciu"; > > i.e. the <&sysmgr_sdr_mmc> clock is actually your "ciu". If I understand your > code correctly, the dw-mshc has exactly two clock inputs, biu and ciu, and > you use sysmgr to provide ciu. The driver code already contains logic to > set the rate of the ciu clock, and you just need to hook into that. Ah yes! This is fantastic. I can definitely just re-use the ciu-clk hook. Thanks! Dinh > > Arnd >
diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt new file mode 100644 index 0000000..c408e74 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt @@ -0,0 +1,38 @@ +* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsys-dw-mshc.txt and the properties used by the SOCFPGA specific +extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: + +* compatible: should be + - "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA + specific extensions. + +* samsung,dw-mshc-sdr-timing: See exynos-dw-mshc.txt for more information about + this property. + +Example: + dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc", "snps,dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>, <&sysmgr_sdr_mmc>; + clock-names = "biu", "ciu", "sysmgr-sdr-mmc"; + num-slots = <1>; + supports-highspeed; + broken-cd; + samsung,dw-mshc-sdr-timing = <3 0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index a6a13b3..5023e25 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -469,6 +469,17 @@ cache-level = <2>; }; + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>, <&sysmgr_sdr_mmc>; + clock-names = "biu", "ciu", "sysmgr-sdr-mmc"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index a8716f6..4ef4fa4 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -28,6 +28,18 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + samsung,dw-mshc-sdr-timing = <3 0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff702000 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index d1ec0ca..25b2653 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -41,6 +41,18 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + samsung,dw-mshc-sdr-timing = <3 0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff700000 { phy-mode = "gmii"; status = "okay";