diff mbox

[2/9] ARM: dts: imx6sl: remove the use of pingrp macros

Message ID 1390668191-20289-3-git-send-email-shawn.guo@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Shawn Guo Jan. 25, 2014, 4:43 p.m. UTC 
We created the pingrp macros in imx6sl-pingrp.h for purpose of less LOC
when same pin group is used by multiple boards.  However, DT maintainers
take it as an abuse of DTC macro support.  So let's get rid of it to
make the pins used by given device more intuitive.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 arch/arm/boot/dts/imx6sl-evk.dts  |  120 ++++++++++++++++++++++++++----
 arch/arm/boot/dts/imx6sl-pingrp.h |  148 -------------------------------------
 arch/arm/boot/dts/imx6sl.dtsi     |    1 -
 3 files changed, 107 insertions(+), 162 deletions(-)
 delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h

Comments

Heiko Stübner Jan. 28, 2014, 10:17 a.m. UTC | #1 
Hi Shawn,

On Sunday, 26. January 2014 00:43:04 Shawn Guo wrote:
> We created the pingrp macros in imx6sl-pingrp.h for purpose of less LOC
> when same pin group is used by multiple boards.  However, DT maintainers
> take it as an abuse of DTC macro support.  So let's get rid of it to
> make the pins used by given device more intuitive.
> 
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
>  arch/arm/boot/dts/imx6sl-evk.dts  |  120 ++++++++++++++++++++++++++----
>  arch/arm/boot/dts/imx6sl-pingrp.h |  148
> ------------------------------------- arch/arm/boot/dts/imx6sl.dtsi     |  
>  1 -
>  3 files changed, 107 insertions(+), 162 deletions(-)
>  delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
> 
> diff --git a/arch/arm/boot/dts/imx6sl-evk.dts
> b/arch/arm/boot/dts/imx6sl-evk.dts index f5e4513..8594d13 100644
> --- a/arch/arm/boot/dts/imx6sl-evk.dts
> +++ b/arch/arm/boot/dts/imx6sl-evk.dts
> @@ -86,55 +86,149 @@
>  		};
> 
>  		pinctrl_ecspi1: ecspi1grp {
> -			fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
> +			fsl,pins = <
> +				MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO	0x100b1
> +				MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x100b1
> +				MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x100b1
> +			>;
>  		};
> 
>  		pinctrl_fec: fecgrp {
> -			fsl,pins = <MX6SL_FEC_PINGRP1>;
> +			fsl,pins = <
> +				MX6SL_PAD_FEC_MDC__FEC_MDC		0x1b0b0
> +				MX6SL_PAD_FEC_MDIO__FEC_MDIO		0x1b0b0
> +				MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV		0x1b0b0
> +				MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0	0x1b0b0
> +				MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1	0x1b0b0
> +				MX6SL_PAD_FEC_TX_EN__FEC_TX_EN		0x1b0b0
> +				MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0	0x1b0b0
> +				MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1	0x1b0b0
> +				MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT	0x4001b0a8
> +			>;
>  		};

[... and so on for the other groups ... ]

I'm confused now :-) . Current linux-next [0] shows the pin-settings as part 
of imx6sl.dtsi - a way a lot of other architectures organize their pingroups 
too, with the board file only referencing the relevant pingroups from the 
predefined ones of the soc.

So I guess your move to the pingrp-header moved them out of the imx6sl.dtsi to 
the .h and is not part of linux-next; but this patch (and the others in this 
series) now moves the definitions into the individual board files. Can't you 
just move them back to the soc-dtsi files to prevent each board duplicating 
them?

Or I've simply missed previous discussions about this ;-) .


Thanks
Heiko

[0] https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm/boot/dts/imx6sl.dtsi#n640
Sascha Hauer Jan. 28, 2014, 11:03 a.m. UTC | #2 
On Tue, Jan 28, 2014 at 11:17:22AM +0100, Heiko Stübner wrote:
> Hi Shawn,
> 
> On Sunday, 26. January 2014 00:43:04 Shawn Guo wrote:
> > We created the pingrp macros in imx6sl-pingrp.h for purpose of less LOC
> > when same pin group is used by multiple boards.  However, DT maintainers
> > take it as an abuse of DTC macro support.  So let's get rid of it to
> > make the pins used by given device more intuitive.
> > 
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> >  arch/arm/boot/dts/imx6sl-evk.dts  |  120 ++++++++++++++++++++++++++----
> >  arch/arm/boot/dts/imx6sl-pingrp.h |  148
> > ------------------------------------- arch/arm/boot/dts/imx6sl.dtsi     |  
> >  1 -
> >  3 files changed, 107 insertions(+), 162 deletions(-)
> >  delete mode 100644 arch/arm/boot/dts/imx6sl-pingrp.h
> > 
> > diff --git a/arch/arm/boot/dts/imx6sl-evk.dts
> > b/arch/arm/boot/dts/imx6sl-evk.dts index f5e4513..8594d13 100644
> > --- a/arch/arm/boot/dts/imx6sl-evk.dts
> > +++ b/arch/arm/boot/dts/imx6sl-evk.dts
> > @@ -86,55 +86,149 @@
> >  		};
> > 
> >  		pinctrl_ecspi1: ecspi1grp {
> > -			fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
> > +			fsl,pins = <
> > +				MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO	0x100b1
> > +				MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x100b1
> > +				MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x100b1
> > +			>;
> >  		};
> > 
> >  		pinctrl_fec: fecgrp {
> > -			fsl,pins = <MX6SL_FEC_PINGRP1>;
> > +			fsl,pins = <
> > +				MX6SL_PAD_FEC_MDC__FEC_MDC		0x1b0b0
> > +				MX6SL_PAD_FEC_MDIO__FEC_MDIO		0x1b0b0
> > +				MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV		0x1b0b0
> > +				MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0	0x1b0b0
> > +				MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1	0x1b0b0
> > +				MX6SL_PAD_FEC_TX_EN__FEC_TX_EN		0x1b0b0
> > +				MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0	0x1b0b0
> > +				MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1	0x1b0b0
> > +				MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT	0x4001b0a8
> > +			>;
> >  		};
> 
> [... and so on for the other groups ... ]
> 
> I'm confused now :-) . Current linux-next [0] shows the pin-settings as part 
> of imx6sl.dtsi - a way a lot of other architectures organize their pingroups 
> too, with the board file only referencing the relevant pingroups from the 
> predefined ones of the soc.

Current mainline has all groups under the iomux node which has the
effect that all possible groups are compiled into every dtb resulting in
very bloated dtbs. So Shawn changed it to what's currently in next, but
this hasn't been accepted by the dt maintainers. Now this series tries
to address the concerns of the dt maintainers by not using macros that
expand to other macros.

Sascha
Shawn Guo Jan. 28, 2014, 11:20 a.m. UTC | #3 
On Tue, Jan 28, 2014 at 11:17:22AM +0100, Heiko Stübner wrote:
> [... and so on for the other groups ... ]
> 
> I'm confused now :-) . Current linux-next [0] shows the pin-settings as part 
> of imx6sl.dtsi - a way a lot of other architectures organize their pingroups 
> too, with the board file only referencing the relevant pingroups from the 
> predefined ones of the soc.
> 
> So I guess your move to the pingrp-header moved them out of the imx6sl.dtsi to 
> the .h and is not part of linux-next;

Yes, my for-next branch was excluded from linux-next temporarily for
some reason.  I will ask Stephen to add it back once v3.14-rc1 is out.
That said, you can see nothing we developed in this cycle on linux-next
for now.

> but this patch (and the others in this 
> series) now moves the definitions into the individual board files. Can't you 
> just move them back to the soc-dtsi files to prevent each board duplicating 
> them?

No.  That will bring back the problem we try to solve from the
beginning [1].

Shawn

[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/275912/
Heiko Stübner Jan. 29, 2014, 10:42 a.m. UTC | #4 
On Tuesday, 28. January 2014 19:20:49 Shawn Guo wrote:
> On Tue, Jan 28, 2014 at 11:17:22AM +0100, Heiko Stübner wrote:
> > [... and so on for the other groups ... ]
> > 
> > I'm confused now :-) . Current linux-next [0] shows the pin-settings as
> > part of imx6sl.dtsi - a way a lot of other architectures organize their
> > pingroups too, with the board file only referencing the relevant
> > pingroups from the predefined ones of the soc.
> > 
> > So I guess your move to the pingrp-header moved them out of the
> > imx6sl.dtsi to the .h and is not part of linux-next;
> 
> Yes, my for-next branch was excluded from linux-next temporarily for
> some reason.  I will ask Stephen to add it back once v3.14-rc1 is out.
> That said, you can see nothing we developed in this cycle on linux-next
> for now.
> 
> > but this patch (and the others in this
> > series) now moves the definitions into the individual board files. Can't
> > you just move them back to the soc-dtsi files to prevent each board
> > duplicating them?
> 
> No.  That will bring back the problem we try to solve from the
> beginning [1].
>
> [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/275912/

Thanks for the pointer, I think I understand the issue now :-) .

So for the short term, I should probably also define the pingroups in my board-
dts then.


But as an insane idea that I just had, because the issue will probably affect 
more architectures at some point when their pingroups or other common-nodes 
grow, how about introducing something like a "/delete-if-unreferenced/" prefix 
in dtc?

As I could see in [0], adding something to dtc is not as far off as I thought.

In essence one would add the pingroups to the soc dtsi, like

		ecspi1 {
			/delete-if-unreferenced/ pinctrl_ecspi1_1: ecspi1grp-1 {
				fsl,pins = <
					MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
					MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
					MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
				>;
			};
		};

and dtc would then be tasked with checking if the node gets referenced in a 
phandle somewhere in the dts and if not removing it.

I don't know if this is at all sane to think about or doable in dtc.


Heiko

[0] http://www.spinics.net/lists/arm-kernel/msg300936.html
diff mbox

Patch

diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index f5e4513..8594d13 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -86,55 +86,149 @@ 
 		};
 
 		pinctrl_ecspi1: ecspi1grp {
-			fsl,pins = <MX6SL_ECSPI1_PINGRP1>;
+			fsl,pins = <
+				MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO	0x100b1
+				MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	0x100b1
+				MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	0x100b1
+			>;
 		};
 
 		pinctrl_fec: fecgrp {
-			fsl,pins = <MX6SL_FEC_PINGRP1>;
+			fsl,pins = <
+				MX6SL_PAD_FEC_MDC__FEC_MDC		0x1b0b0
+				MX6SL_PAD_FEC_MDIO__FEC_MDIO		0x1b0b0
+				MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV		0x1b0b0
+				MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0	0x1b0b0
+				MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1	0x1b0b0
+				MX6SL_PAD_FEC_TX_EN__FEC_TX_EN		0x1b0b0
+				MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0	0x1b0b0
+				MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1	0x1b0b0
+				MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT	0x4001b0a8
+			>;
 		};
 
 		pinctrl_uart1: uart1grp {
-			fsl,pins = <MX6SL_UART1_PINGRP1>;
+			fsl,pins = <
+				MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x1b0b1
+				MX6SL_PAD_UART1_TXD__UART1_TX_DATA	0x1b0b1
+			>;
 		};
 
 		pinctrl_usbotg1: usbotg1grp {
-			fsl,pins = <MX6SL_USBOTG1_PINGRP1>;
+			fsl,pins = <
+				MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID	0x17059
+			>;
 		};
 
 		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <MX6SL_USDHC1_PINGRP_D8>;
+			fsl,pins = <
+				MX6SL_PAD_SD1_CMD__SD1_CMD		0x17059
+				MX6SL_PAD_SD1_CLK__SD1_CLK		0x10059
+				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x17059
+				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x17059
+				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x17059
+				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x17059
+				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x17059
+				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x17059
+				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x17059
+				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x17059
+			>;
 		};
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-			fsl,pins = <MX6SL_USDHC1_PINGRP_D8_100MHZ>;
+			fsl,pins = <
+				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170b9
+				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100b9
+				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170b9
+				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170b9
+				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170b9
+				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170b9
+				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170b9
+				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170b9
+				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170b9
+				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170b9
+			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-			fsl,pins = <MX6SL_USDHC1_PINGRP_D8_200MHZ>;
+			fsl,pins = <
+				MX6SL_PAD_SD1_CMD__SD1_CMD		0x170f9
+				MX6SL_PAD_SD1_CLK__SD1_CLK		0x100f9
+				MX6SL_PAD_SD1_DAT0__SD1_DATA0		0x170f9
+				MX6SL_PAD_SD1_DAT1__SD1_DATA1		0x170f9
+				MX6SL_PAD_SD1_DAT2__SD1_DATA2		0x170f9
+				MX6SL_PAD_SD1_DAT3__SD1_DATA3		0x170f9
+				MX6SL_PAD_SD1_DAT4__SD1_DATA4		0x170f9
+				MX6SL_PAD_SD1_DAT5__SD1_DATA5		0x170f9
+				MX6SL_PAD_SD1_DAT6__SD1_DATA6		0x170f9
+				MX6SL_PAD_SD1_DAT7__SD1_DATA7		0x170f9
+			>;
 		};
 
 		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <MX6SL_USDHC2_PINGRP_D4>;
+			fsl,pins = <
+				MX6SL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6SL_PAD_SD2_CLK__SD2_CLK		0x10059
+				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			>;
 		};
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
-			fsl,pins = <MX6SL_USDHC2_PINGRP_D4_100MHZ>;
+			fsl,pins = <
+				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170b9
+				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100b9
+				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
+				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
+				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
+				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
+			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
-			fsl,pins = <MX6SL_USDHC2_PINGRP_D4_200MHZ>;
+			fsl,pins = <
+				MX6SL_PAD_SD2_CMD__SD2_CMD		0x170f9
+				MX6SL_PAD_SD2_CLK__SD2_CLK		0x100f9
+				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
+				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
+				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
+				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
+			>;
 		};
 
 		pinctrl_usdhc3: usdhc3grp {
-			fsl,pins = <MX6SL_USDHC3_PINGRP_D4>;
+			fsl,pins = <
+				MX6SL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6SL_PAD_SD3_CLK__SD3_CLK		0x10059
+				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+			>;
 		};
 
 		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
-			fsl,pins = <MX6SL_USDHC3_PINGRP_D4_100MHZ>;
+			fsl,pins = <
+				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170b9
+				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100b9
+				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
+				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
+				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
+				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
+			>;
 		};
 
 		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
-			fsl,pins = <MX6SL_USDHC3_PINGRP_D4_200MHZ>;
+			fsl,pins = <
+				MX6SL_PAD_SD3_CMD__SD3_CMD		0x170f9
+				MX6SL_PAD_SD3_CLK__SD3_CLK		0x100f9
+				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
+				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
+				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
+				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
+			>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/imx6sl-pingrp.h b/arch/arm/boot/dts/imx6sl-pingrp.h
deleted file mode 100644
index ead26d4..0000000
--- a/arch/arm/boot/dts/imx6sl-pingrp.h
+++ /dev/null
@@ -1,148 +0,0 @@ 
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __DTS_IMX6SL_PINGRP_H
-#define __DTS_IMX6SL_PINGRP_H
-
-#define MX6SL_ECSPI1_PINGRP1 \
-	MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO		0x100b1 \
-	MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI		0x100b1 \
-	MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK		0x100b1
-
-#define MX6SL_FEC_PINGRP1 \
-	MX6SL_PAD_FEC_MDC__FEC_MDC			0x1b0b0 \
-	MX6SL_PAD_FEC_MDIO__FEC_MDIO			0x1b0b0 \
-	MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV			0x1b0b0 \
-	MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0		0x1b0b0 \
-	MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1		0x1b0b0 \
-	MX6SL_PAD_FEC_TX_EN__FEC_TX_EN			0x1b0b0 \
-	MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0		0x1b0b0 \
-	MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1		0x1b0b0 \
-	MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT		0x4001b0a8
-
-#define MX6SL_UART1_PINGRP1 \
-	MX6SL_PAD_UART1_RXD__UART1_RX_DATA		0x1b0b1 \
-	MX6SL_PAD_UART1_TXD__UART1_TX_DATA		0x1b0b1
-
-#define MX6SL_USBOTG1_PINGRP1 \
-	MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID		0x17059
-
-#define MX6SL_USBOTG1_PINGRP2 \
-	MX6SL_PAD_FEC_RXD0__USB_OTG1_ID			0x17059
-
-#define MX6SL_USBOTG1_PINGRP3 \
-	MX6SL_PAD_LCD_DAT1__USB_OTG1_ID			0x17059
-
-#define MX6SL_USBOTG1_PINGRP4 \
-	MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID		0x17059
-
-#define MX6SL_USBOTG1_PINGRP5 \
-	MX6SL_PAD_SD3_DAT0__USB_OTG1_ID			0x17059
-
-#define MX6SL_USBOTG2_PINGRP1 \
-	MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC		0x17059
-
-#define MX6SL_USBOTG2_PINGRP2 \
-	MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC		0x17059
-
-#define MX6SL_USBOTG2_PINGRP3 \
-	MX6SL_PAD_KEY_ROW5__USB_OTG2_OC			0x17059
-
-#define MX6SL_USBOTG2_PINGRP4 \
-	MX6SL_PAD_SD3_DAT2__USB_OTG2_OC			0x17059
-
-#define MX6SL_USDHC1_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_SD1_CMD__SD1_CMD			pad \
-	MX6SL_PAD_SD1_CLK__SD1_CLK			pad_clk \
-	MX6SL_PAD_SD1_DAT0__SD1_DATA0			pad \
-	MX6SL_PAD_SD1_DAT1__SD1_DATA1			pad \
-	MX6SL_PAD_SD1_DAT2__SD1_DATA2			pad \
-	MX6SL_PAD_SD1_DAT3__SD1_DATA3			pad_data3
-
-#define MX6SL_USDHC1_D8(pad, pad_data3, pad_clk)	\
-	MX6SL_USDHC1_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_SD1_DAT4__SD1_DATA4			pad \
-	MX6SL_PAD_SD1_DAT5__SD1_DATA5			pad \
-	MX6SL_PAD_SD1_DAT6__SD1_DATA6			pad \
-	MX6SL_PAD_SD1_DAT7__SD1_DATA7			pad
-
-#define MX6SL_USDHC2_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_SD2_CMD__SD2_CMD			pad \
-	MX6SL_PAD_SD2_CLK__SD2_CLK			pad_clk \
-	MX6SL_PAD_SD2_DAT0__SD2_DATA0			pad \
-	MX6SL_PAD_SD2_DAT1__SD2_DATA1			pad \
-	MX6SL_PAD_SD2_DAT2__SD2_DATA2			pad \
-	MX6SL_PAD_SD2_DAT3__SD2_DATA3			pad_data3
-
-#define MX6SL_USDHC2_D8(pad, pad_data3, pad_clk)	\
-	MX6SL_USDHC2_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_SD2_DAT4__SD2_DATA4			pad \
-	MX6SL_PAD_SD2_DAT5__SD2_DATA5			pad \
-	MX6SL_PAD_SD2_DAT6__SD2_DATA6			pad \
-	MX6SL_PAD_SD2_DAT7__SD2_DATA7			pad
-
-#define MX6SL_USDHC3_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_SD3_CMD__SD3_CMD			pad \
-	MX6SL_PAD_SD3_CLK__SD3_CLK			pad_clk \
-	MX6SL_PAD_SD3_DAT0__SD3_DATA0			pad \
-	MX6SL_PAD_SD3_DAT1__SD3_DATA1			pad \
-	MX6SL_PAD_SD3_DAT2__SD3_DATA2			pad \
-	MX6SL_PAD_SD3_DAT3__SD3_DATA3			pad_data3
-
-#define MX6SL_USDHC3_D8(pad, pad_data3, pad_clk)	\
-	MX6SL_USDHC3_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_SD2_DAT4__SD3_DATA4			pad \
-	MX6SL_PAD_SD2_DAT5__SD3_DATA5			pad \
-	MX6SL_PAD_SD2_DAT6__SD3_DATA6			pad \
-	MX6SL_PAD_SD2_DAT7__SD3_DATA7			pad
-
-#define MX6SL_USDHC4_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_EPDC_BDR1__SD4_CMD			pad \
-	MX6SL_PAD_EPDC_BDR0__SD4_CLK			pad_clk \
-	MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0		pad \
-	MX6SL_PAD_EPDC_PWRINT__SD4_DATA1		pad \
-	MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2		pad \
-	MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3		pad_data3
-
-#define MX6SL_USDHC4_D8(pad, pad_data3, pad_clk)	\
-	MX6SL_USDHC4_D4(pad, pad_data3, pad_clk)	\
-	MX6SL_PAD_KEY_COL7__SD4_DATA4			pad \
-	MX6SL_PAD_KEY_ROW7__SD4_DATA5			pad \
-	MX6SL_PAD_KEY_COL3__SD4_DATA6			pad \
-	MX6SL_PAD_KEY_ROW3__SD4_DATA7			pad
-
-#define MX6SL_USDHC1_PINGRP_D4	      MX6SL_USDHC1_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC1_PINGRP_D4_100MHZ MX6SL_USDHC1_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC1_PINGRP_D4_200MHZ MX6SL_USDHC1_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC1_PINGRP_D8	      MX6SL_USDHC1_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC1_PINGRP_D8_100MHZ MX6SL_USDHC1_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC1_PINGRP_D8_200MHZ MX6SL_USDHC1_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC2_PINGRP_D4	      MX6SL_USDHC2_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC2_PINGRP_D4_100MHZ MX6SL_USDHC2_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC2_PINGRP_D4_200MHZ MX6SL_USDHC2_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC2_PINGRP_D8	      MX6SL_USDHC2_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC2_PINGRP_D8_100MHZ MX6SL_USDHC2_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC2_PINGRP_D8_200MHZ MX6SL_USDHC2_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC3_PINGRP_D4	      MX6SL_USDHC3_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC3_PINGRP_D4_100MHZ MX6SL_USDHC3_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC3_PINGRP_D4_200MHZ MX6SL_USDHC3_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC3_PINGRP_D8	      MX6SL_USDHC3_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC3_PINGRP_D8_100MHZ MX6SL_USDHC3_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC3_PINGRP_D8_200MHZ MX6SL_USDHC3_D8(0x170f9, 0x170f9, 0x100f9)
-
-#define MX6SL_USDHC4_PINGRP_D4	      MX6SL_USDHC4_D4(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC4_PINGRP_D4_100MHZ MX6SL_USDHC4_D4(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC4_PINGRP_D4_200MHZ MX6SL_USDHC4_D4(0x170f9, 0x170f9, 0x100f9)
-#define MX6SL_USDHC4_PINGRP_D8	      MX6SL_USDHC4_D8(0x17059, 0x17059, 0x10059)
-#define MX6SL_USDHC4_PINGRP_D8_100MHZ MX6SL_USDHC4_D8(0x170b9, 0x170b9, 0x100b9)
-#define MX6SL_USDHC4_PINGRP_D8_200MHZ MX6SL_USDHC4_D8(0x170f9, 0x170f9, 0x100f9)
-
-#endif /* __DTS_IMX6SL_PINGRP_H */
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 2ed687c..2b7641a 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -10,7 +10,6 @@ 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "skeleton.dtsi"
 #include "imx6sl-pinfunc.h"
-#include "imx6sl-pingrp.h"
 #include <dt-bindings/clock/imx6sl-clock.h>
 
 / {