| Message ID | 1391608060-10760-3-git-send-email-ivan.khoronzhuk@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> wrote: > This patch provides bindings for the 64-bit timer in the KeyStone > architecture devices. The timer can be configured as a general-purpose 64-bit > timer, dual general-purpose 32-bit timers. When configured as dual 32-bit > timers, each half can operate in conjunction (chain mode) or independently > (unchained mode) of each other. This is software configurable or h/w design time configurations? Rob > > It is global timer is a free running up-counter and can generate interrupt > when the counter reaches preset counter values. > > Documentation: > http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf > > Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> > --- > .../bindings/timer/ti,keystone-timer.txt | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/ti,keystone-timer.txt > > diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt > new file mode 100644 > index 0000000..5fbe361 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt > @@ -0,0 +1,29 @@ > +* Device tree bindings for Texas instruments Keystone timer > + > +This document provides bindings for the 64-bit timer in the KeyStone > +architecture devices. The timer can be configured as a general-purpose 64-bit > +timer, dual general-purpose 32-bit timers. When configured as dual 32-bit > +timers, each half can operate in conjunction (chain mode) or independently > +(unchained mode) of each other. > + > +It is global timer is a free running up-counter and can generate interrupt > +when the counter reaches preset counter values. > + > +Documentation: > +http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf > + > +Required properties: > + > +- compatible : should be "ti,keystone-timer". > +- reg : specifies base physical address and count of the registers. > +- interrupts : interrupt generated by the timer. > +- clocks : the clock feeding the timer clock. > + > +Example: > + > +timer@22f0000 { > + compatible = "ti,keystone-timer"; > + reg = <0x022f0000 0x80>; > + interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; > + clocks = <&clktimer15>; > +}; > -- > 1.8.3.2 >
On 02/05/2014 04:39 PM, Rob Herring wrote: > On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> wrote: >> This patch provides bindings for the 64-bit timer in the KeyStone >> architecture devices. The timer can be configured as a general-purpose 64-bit >> timer, dual general-purpose 32-bit timers. When configured as dual 32-bit >> timers, each half can operate in conjunction (chain mode) or independently >> (unchained mode) of each other. > This is software configurable or h/w design time configurations? > > Rob > This is h/w design time configurations
On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> wrote: > > On 02/05/2014 04:39 PM, Rob Herring wrote: >> >> On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> >> wrote: >>> >>> This patch provides bindings for the 64-bit timer in the KeyStone >>> architecture devices. The timer can be configured as a general-purpose >>> 64-bit >>> timer, dual general-purpose 32-bit timers. When configured as dual 32-bit >>> timers, each half can operate in conjunction (chain mode) or >>> independently >>> (unchained mode) of each other. >> >> This is software configurable or h/w design time configurations? >> >> Rob >> > > This is h/w design time configurations Then it seems like the binding should provide for describing those differences either with a property or different compatible strings. Rob
On 02/05/2014 07:41 PM, Rob Herring wrote: > On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> wrote: >> On 02/05/2014 04:39 PM, Rob Herring wrote: >>> On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> >>> wrote: >>>> This patch provides bindings for the 64-bit timer in the KeyStone >>>> architecture devices. The timer can be configured as a general-purpose >>>> 64-bit >>>> timer, dual general-purpose 32-bit timers. When configured as dual 32-bit >>>> timers, each half can operate in conjunction (chain mode) or >>>> independently >>>> (unchained mode) of each other. >>> This is software configurable or h/w design time configurations? >>> >>> Rob >>> >> This is h/w design time configurations > Then it seems like the binding should provide for describing those > differences either with a property or different compatible strings. > > Rob Oh..sorry, seems I didn't catch, this is configurable by software. These configurations are like modes in which timer can work and they are not different hardware IPs. It depends on driver in which mode it should work.
On Wed, Feb 5, 2014 at 12:52 PM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> wrote: > > On 02/05/2014 07:41 PM, Rob Herring wrote: >> >> On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> >> wrote: >>> >>> On 02/05/2014 04:39 PM, Rob Herring wrote: >>>> >>>> On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> >>>> wrote: >>>>> >>>>> This patch provides bindings for the 64-bit timer in the KeyStone >>>>> architecture devices. The timer can be configured as a general-purpose >>>>> 64-bit >>>>> timer, dual general-purpose 32-bit timers. When configured as dual >>>>> 32-bit >>>>> timers, each half can operate in conjunction (chain mode) or >>>>> independently >>>>> (unchained mode) of each other. >>>> >>>> This is software configurable or h/w design time configurations? >>>> >>>> Rob >>>> >>> This is h/w design time configurations >> >> Then it seems like the binding should provide for describing those >> differences either with a property or different compatible strings. >> >> Rob > > Oh..sorry, seems I didn't catch, this is configurable by software. > These configurations are like modes in which timer can work > and they are not different hardware IPs. It depends on driver in > which mode it should work. In that case, Acked-by: Rob Herring <robh@kernel.org>
On 02/06/2014 01:36 AM, Rob Herring wrote: > On Wed, Feb 5, 2014 at 12:52 PM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> wrote: >> On 02/05/2014 07:41 PM, Rob Herring wrote: >>> On Wed, Feb 5, 2014 at 10:18 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> >>> wrote: >>>> On 02/05/2014 04:39 PM, Rob Herring wrote: >>>>> On Wed, Feb 5, 2014 at 7:47 AM, Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> >>>>> wrote: >>>>>> This patch provides bindings for the 64-bit timer in the KeyStone >>>>>> architecture devices. The timer can be configured as a general-purpose >>>>>> 64-bit >>>>>> timer, dual general-purpose 32-bit timers. When configured as dual >>>>>> 32-bit >>>>>> timers, each half can operate in conjunction (chain mode) or >>>>>> independently >>>>>> (unchained mode) of each other. >>>>> This is software configurable or h/w design time configurations? >>>>> >>>>> Rob >>>>> >>>> This is h/w design time configurations >>> Then it seems like the binding should provide for describing those >>> differences either with a property or different compatible strings. >>> >>> Rob >> Oh..sorry, seems I didn't catch, this is configurable by software. >> These configurations are like modes in which timer can work >> and they are not different hardware IPs. It depends on driver in >> which mode it should work. > In that case, > > Acked-by: Rob Herring <robh@kernel.org> Thanks
diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt new file mode 100644 index 0000000..5fbe361 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt @@ -0,0 +1,29 @@ +* Device tree bindings for Texas instruments Keystone timer + +This document provides bindings for the 64-bit timer in the KeyStone +architecture devices. The timer can be configured as a general-purpose 64-bit +timer, dual general-purpose 32-bit timers. When configured as dual 32-bit +timers, each half can operate in conjunction (chain mode) or independently +(unchained mode) of each other. + +It is global timer is a free running up-counter and can generate interrupt +when the counter reaches preset counter values. + +Documentation: +http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf + +Required properties: + +- compatible : should be "ti,keystone-timer". +- reg : specifies base physical address and count of the registers. +- interrupts : interrupt generated by the timer. +- clocks : the clock feeding the timer clock. + +Example: + +timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; + clocks = <&clktimer15>; +};