| Message ID | 1391032514-19136-5-git-send-email-bradley.d.volkin@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote: > From: Brad Volkin <bradley.d.volkin@intel.com> > > The spec defines most of these commands as privileged. A few others, > like the semaphore mbox command and some display commands, are also > reserved for the driver's use. Subsequent patches relax some of > these restrictions. > > Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com> > --- > drivers/gpu/drm/i915/i915_cmd_parser.c | 54 ++++++++++++++++++++++++---------- > drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++---------- > 2 files changed, 54 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 2e27bad..cc2f68c 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -57,27 +57,27 @@ > static const struct drm_i915_cmd_descriptor common_cmds[] = { > CMD( MI_NOOP, SMI, F, 1, S ), > CMD( MI_USER_INTERRUPT, SMI, F, 1, S ), > - CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ), > + CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ), > CMD( MI_ARB_CHECK, SMI, F, 1, S ), > CMD( MI_REPORT_HEAD, SMI, F, 1, S ), > CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), > - CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, S ), > - CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, S ), > - CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, S ), > - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, S ), > - CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, S ), > + CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), > + CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), > + CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ), > + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ), > + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ), > CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), > }; > > static const struct drm_i915_cmd_descriptor render_cmds[] = { > CMD( MI_FLUSH, SMI, F, 1, S ), > - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), > + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), > CMD( MI_PREDICATE, SMI, F, 1, S ), > CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), > - CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ), > - CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, S ), > + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), > + CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), > CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), > - CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, S ), > + CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), > CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ), > CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), > CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), > @@ -92,7 +92,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { > CMD( MI_RS_CONTROL, SMI, F, 1, S ), > CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), > CMD( MI_RS_CONTEXT, SMI, F, 1, S ), > - CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, S ), > + CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), > + CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), > + CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), > CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), > CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), > CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), > @@ -107,8 +109,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { > }; > > static const struct drm_i915_cmd_descriptor video_cmds[] = { > - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), > + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), > CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ), > + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), > CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), > /* > * MFX_WAIT doesn't fit the way we handle length for most commands. > @@ -119,18 +122,25 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = { > }; > > static const struct drm_i915_cmd_descriptor vecs_cmds[] = { > - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), > + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), > CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ), > + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), > CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), > }; > > static const struct drm_i915_cmd_descriptor blt_cmds[] = { > - CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ), > + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), > CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ), > + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), > CMD( COLOR_BLT, S2D, !F, 0x3F, S ), > CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), > }; > > +static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { > + CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), > + CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), > +}; > + > #undef CMD > #undef SMI > #undef S3D > @@ -169,6 +179,12 @@ static const struct drm_i915_cmd_table gen7_blt_cmds[] = { > { blt_cmds, ARRAY_SIZE(blt_cmds) }, > }; > > +static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { > + { common_cmds, ARRAY_SIZE(common_cmds) }, > + { blt_cmds, ARRAY_SIZE(blt_cmds) }, > + { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, > +}; > + > #define CLIENT_MASK 0xE0000000 > #define SUBCLIENT_MASK 0x18000000 > #define MI_CLIENT 0x00000000 > @@ -305,8 +321,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring) > ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; > break; > case BCS: > - ring->cmd_tables = gen7_blt_cmds; > - ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); > + if (IS_HASWELL(ring->dev)) { > + ring->cmd_tables = hsw_blt_ring_cmds; > + ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); > + } else { > + ring->cmd_tables = gen7_blt_cmds; > + ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); > + } > + > ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; > break; > case VECS: > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 13ed6ed..2b7c26e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -339,21 +339,22 @@ > /* > * Commands used only by the command parser > */ > -#define MI_SET_PREDICATE MI_INSTR(0x01, 0) > -#define MI_ARB_CHECK MI_INSTR(0x05, 0) > -#define MI_RS_CONTROL MI_INSTR(0x06, 0) > -#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) > -#define MI_PREDICATE MI_INSTR(0x0C, 0) > -#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) > -#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) > -#define MI_URB_CLEAR MI_INSTR(0x19, 0) > -#define MI_UPDATE_GTT MI_INSTR(0x23, 0) > -#define MI_CLFLUSH MI_INSTR(0x27, 0) > -#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) > -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) > -#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) > -#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) > -#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) > +#define MI_SET_PREDICATE MI_INSTR(0x01, 0) > +#define MI_ARB_CHECK MI_INSTR(0x05, 0) > +#define MI_RS_CONTROL MI_INSTR(0x06, 0) > +#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) > +#define MI_PREDICATE MI_INSTR(0x0C, 0) > +#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) > +#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) > +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) > +#define MI_URB_CLEAR MI_INSTR(0x19, 0) > +#define MI_UPDATE_GTT MI_INSTR(0x23, 0) > +#define MI_CLFLUSH MI_INSTR(0x27, 0) > +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) > +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) > +#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) > +#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) > +#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) Superfluous whitespace change hunk. > #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) > > #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) > -- > 1.8.5.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[snip] On Wed, Feb 05, 2014 at 07:22:33AM -0800, Jani Nikula wrote: > On Wed, 29 Jan 2014, bradley.d.volkin@intel.com wrote: > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 13ed6ed..2b7c26e 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -339,21 +339,22 @@ > > /* > > * Commands used only by the command parser > > */ > > -#define MI_SET_PREDICATE MI_INSTR(0x01, 0) > > -#define MI_ARB_CHECK MI_INSTR(0x05, 0) > > -#define MI_RS_CONTROL MI_INSTR(0x06, 0) > > -#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) > > -#define MI_PREDICATE MI_INSTR(0x0C, 0) > > -#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) > > -#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) > > -#define MI_URB_CLEAR MI_INSTR(0x19, 0) > > -#define MI_UPDATE_GTT MI_INSTR(0x23, 0) > > -#define MI_CLFLUSH MI_INSTR(0x27, 0) > > -#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) > > -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) > > -#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) > > -#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) > > -#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) > > +#define MI_SET_PREDICATE MI_INSTR(0x01, 0) > > +#define MI_ARB_CHECK MI_INSTR(0x05, 0) > > +#define MI_RS_CONTROL MI_INSTR(0x06, 0) > > +#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) > > +#define MI_PREDICATE MI_INSTR(0x0C, 0) > > +#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) > > +#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) > > +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) > > +#define MI_URB_CLEAR MI_INSTR(0x19, 0) > > +#define MI_UPDATE_GTT MI_INSTR(0x23, 0) > > +#define MI_CLFLUSH MI_INSTR(0x27, 0) > > +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) > > +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) > > +#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) > > +#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) > > +#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) > > Superfluous whitespace change hunk. It adds MI_LOAD_SCAN_LINES_EXCL and adjusts the whitespace to line up. I see that the whitespace change makes the actual change less obvious. I'll try to clean that up. - Brad > > > > #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) > > > > #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) > > -- > > 1.8.5.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Technology Center
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 2e27bad..cc2f68c 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -57,27 +57,27 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = { CMD( MI_NOOP, SMI, F, 1, S ), CMD( MI_USER_INTERRUPT, SMI, F, 1, S ), - CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ), + CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ), CMD( MI_ARB_CHECK, SMI, F, 1, S ), CMD( MI_REPORT_HEAD, SMI, F, 1, S ), CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), - CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, S ), - CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, S ), - CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, S ), - CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, S ), - CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, S ), + CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), + CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), + CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ), + CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ), + CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ), CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), }; static const struct drm_i915_cmd_descriptor render_cmds[] = { CMD( MI_FLUSH, SMI, F, 1, S ), - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), CMD( MI_PREDICATE, SMI, F, 1, S ), CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), - CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ), - CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, S ), + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), + CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), - CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, S ), + CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), CMD( MI_CLFLUSH, SMI, !F, 0x3FF, S ), CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), @@ -92,7 +92,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { CMD( MI_RS_CONTROL, SMI, F, 1, S ), CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), CMD( MI_RS_CONTEXT, SMI, F, 1, S ), - CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, S ), + CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), + CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), + CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), @@ -107,8 +109,9 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { }; static const struct drm_i915_cmd_descriptor video_cmds[] = { - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ), + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), /* * MFX_WAIT doesn't fit the way we handle length for most commands. @@ -119,18 +122,25 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = { }; static const struct drm_i915_cmd_descriptor vecs_cmds[] = { - CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), + CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, S ), + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ), }; static const struct drm_i915_cmd_descriptor blt_cmds[] = { - CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, S ), + CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ), + CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), CMD( COLOR_BLT, S2D, !F, 0x3F, S ), CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), }; +static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { + CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), + CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), +}; + #undef CMD #undef SMI #undef S3D @@ -169,6 +179,12 @@ static const struct drm_i915_cmd_table gen7_blt_cmds[] = { { blt_cmds, ARRAY_SIZE(blt_cmds) }, }; +static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { + { common_cmds, ARRAY_SIZE(common_cmds) }, + { blt_cmds, ARRAY_SIZE(blt_cmds) }, + { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, +}; + #define CLIENT_MASK 0xE0000000 #define SUBCLIENT_MASK 0x18000000 #define MI_CLIENT 0x00000000 @@ -305,8 +321,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring) ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; break; case BCS: - ring->cmd_tables = gen7_blt_cmds; - ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); + if (IS_HASWELL(ring->dev)) { + ring->cmd_tables = hsw_blt_ring_cmds; + ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); + } else { + ring->cmd_tables = gen7_blt_cmds; + ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); + } + ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; break; case VECS: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 13ed6ed..2b7c26e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -339,21 +339,22 @@ /* * Commands used only by the command parser */ -#define MI_SET_PREDICATE MI_INSTR(0x01, 0) -#define MI_ARB_CHECK MI_INSTR(0x05, 0) -#define MI_RS_CONTROL MI_INSTR(0x06, 0) -#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) -#define MI_PREDICATE MI_INSTR(0x0C, 0) -#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) -#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) -#define MI_URB_CLEAR MI_INSTR(0x19, 0) -#define MI_UPDATE_GTT MI_INSTR(0x23, 0) -#define MI_CLFLUSH MI_INSTR(0x27, 0) -#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) -#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) -#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) -#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) +#define MI_SET_PREDICATE MI_INSTR(0x01, 0) +#define MI_ARB_CHECK MI_INSTR(0x05, 0) +#define MI_RS_CONTROL MI_INSTR(0x06, 0) +#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) +#define MI_PREDICATE MI_INSTR(0x0C, 0) +#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) +#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) +#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) +#define MI_URB_CLEAR MI_INSTR(0x19, 0) +#define MI_UPDATE_GTT MI_INSTR(0x23, 0) +#define MI_CLFLUSH MI_INSTR(0x27, 0) +#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) +#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) +#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) +#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))