| Message ID | 1393608523-17509-8-git-send-email-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | Awaiting Upstream |
| Headers | show |
On Friday 28 February 2014, Lucas Stach wrote: > +Required properties: > +- compatible: "fsl,imx6q-pcie" > +- reg: base addresse and length of the pcie controller > +- interrupts: First entry must contain interrupt handle for controller > + INTA output. I think this should be documented as "optional" and only for backwards compatibility with old kernels. > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - "pcie_ref_125m" > + - "sata_ref_100m" > + - "lvds_gate" > + - "pcie_axi" I don't understand why you have completely different clocks here from the exynos documentation. The clock names should really be the same. Also, why do you have a "sata_ref_100m" clock? Is this just driving a device that happens to be on-board for a specific machine? Same for the "lvds_gate". Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Feb 28, 2014 at 9:28 AM, Lucas Stach <l.stach@pengutronix.de> wrote: > The glue around the core designware IP is > significantly different between the Exynos and > i.MX, which is reflected in the DT bindings. > > Note that this patch doesn't change any bindings, > but just alters the documentation to match reality > of deployed DTs and kernels. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > .../devicetree/bindings/pci/designware-pcie.txt | 69 +-------------------- > .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 48 +++++++++++++++ > .../bindings/pci/samsung,exynos5440-pcie.txt | 70 ++++++++++++++++++++++ > 3 files changed, 119 insertions(+), 68 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt > > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt > index d6fae13ff062..8274c80fe874 100644 > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt > @@ -1,15 +1,7 @@ > * Synopsys Designware PCIe interface > > Required properties: > -- compatible: should contain "snps,dw-pcie" to identify the > - core, plus an identifier for the specific instance, such > - as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie". > -- reg: base addresses and lengths of the pcie controller, > - the phy controller, additional register for the phy controller. > -- interrupts: interrupt values for level interrupt, > - pulse interrupt, special interrupt. > -- clocks: from common clock binding: handle to pci clock. > -- clock-names: from common clock binding: should be "pcie" and "pcie_bus". > +- compatible: should contain "snps,dw-pcie" to identify the core. > - #address-cells: set to <3> > - #size-cells: set to <2> > - device_type: set to "pci" > @@ -22,62 +14,3 @@ Required properties: > > Optional properties: > - reset-gpio: gpio pin number of power good signal > - > -Optional properties for fsl,imx6q-pcie > -- power-on-gpio: gpio pin number of power-enable signal > -- wake-up-gpio: gpio pin number of incoming wakeup signal > -- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal > - > -Example: > - > -SoC specific DT Entry: > - > - pcie@290000 { > - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; > - reg = <0x290000 0x1000 > - 0x270000 0x1000 > - 0x271000 0x40>; > - interrupts = <0 20 0>, <0 21 0>, <0 22 0>; > - clocks = <&clock 28>, <&clock 27>; > - clock-names = "pcie", "pcie_bus"; > - #address-cells = <3>; > - #size-cells = <2>; > - device_type = "pci"; > - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ > - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ > - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0x0 0 &gic 53>; > - num-lanes = <4>; > - }; > - > - pcie@2a0000 { > - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; > - reg = <0x2a0000 0x1000 > - 0x272000 0x1000 > - 0x271040 0x40>; > - interrupts = <0 23 0>, <0 24 0>, <0 25 0>; > - clocks = <&clock 29>, <&clock 27>; > - clock-names = "pcie", "pcie_bus"; > - #address-cells = <3>; > - #size-cells = <2>; > - device_type = "pci"; > - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ > - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ > - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ > - #interrupt-cells = <1>; > - interrupt-map-mask = <0 0 0 0>; > - interrupt-map = <0x0 0 &gic 56>; > - num-lanes = <4>; > - }; > - > -Board specific DT Entry: > - > - pcie@290000 { > - reset-gpio = <&pin_ctrl 5 0>; > - }; > - > - pcie@2a0000 { > - reset-gpio = <&pin_ctrl 22 0>; > - }; > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > new file mode 100644 > index 000000000000..93fbfd62f13c > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > @@ -0,0 +1,48 @@ > +* Freescale i.MX6 PCIe interface > + > +This PCIe host controller is based on the Synopsis Designware PCIe IP > +and thus inherits all the common properties defined in designware-pcie.txt. > + > +Required properties: > +- compatible: "fsl,imx6q-pcie" > +- reg: base addresse and length of the pcie controller > +- interrupts: First entry must contain interrupt handle for controller > + INTA output. > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - "pcie_ref_125m" > + - "sata_ref_100m" > + - "lvds_gate" > + - "pcie_axi" > + > +Optional properties: > +- power-on-gpio: gpio pin number of power-enable signal > +- wake-up-gpio: gpio pin number of incoming wakeup signal > +- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal > + > +Example: > + > + pcie@0x01000000 { > + compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; > + reg = <0x01ffc000 0x4000>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 > + 0x81000000 0 0 0x01f80000 0 0x00010000 > + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; > + num-lanes = <1>; > + > + interrupts = <0 123 0x04>; Lucas, I'm still trying to understand DT interrupt specification and mapping. Should this be: interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH> It seems there is a lot of mixed use of numbers vs defines from linux/include/dt-bindings in dts files for both gpio and interrupt levels. Thanks, Tim > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; > + clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; > + }; > diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt > new file mode 100644 > index 000000000000..0b4de1014876 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt > @@ -0,0 +1,70 @@ > +* Samsung Exynos 5440 PCIe interface > + > +This PCIe host controller is based on the Synopsis Designware PCIe IP > +and thus inherits all the common properties defined in designware-pcie.txt. > + > +Required properties: > +- compatible: "samsung,exynos5440-pcie" > +- reg: base addresses and lengths of the pcie controller, > + the phy controller, additional register for the phy controller. > +- interrupts: A list of interrupt outputs for level interrupt, > + pulse interrupt, special interrupt. > +- clocks: Must contain an entry for each entry in clock-names. > + See ../clocks/clock-bindings.txt for details. > +- clock-names: Must include the following entries: > + - "pcie" > + - "pcie_bus" > + > +Example: > + > +SoC specific DT Entry: > + > + pcie@290000 { > + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; > + reg = <0x290000 0x1000 > + 0x270000 0x1000 > + 0x271000 0x40>; > + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; > + clocks = <&clock 28>, <&clock 27>; > + clock-names = "pcie", "pcie_bus"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ > + 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ > + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + num-lanes = <4>; > + }; > + > + pcie@2a0000 { > + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; > + reg = <0x2a0000 0x1000 > + 0x272000 0x1000 > + 0x271040 0x40>; > + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; > + clocks = <&clock 29>, <&clock 27>; > + clock-names = "pcie", "pcie_bus"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ > + 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ > + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0>; > + interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; > + num-lanes = <4>; > + }; > + > +Board specific DT Entry: > + > + pcie@290000 { > + reset-gpio = <&pin_ctrl 5 0>; > + }; > + > + pcie@2a0000 { > + reset-gpio = <&pin_ctrl 22 0>; > + }; > -- > 1.8.5.3 > -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Am Freitag, den 28.02.2014, 21:03 +0100 schrieb Arnd Bergmann: > On Friday 28 February 2014, Lucas Stach wrote: > > +Required properties: > > +- compatible: "fsl,imx6q-pcie" > > +- reg: base addresse and length of the pcie controller > > +- interrupts: First entry must contain interrupt handle for controller > > + INTA output. > > I think this should be documented as "optional" and only for > backwards compatibility with old kernels. > > > +- clocks: Must contain an entry for each entry in clock-names. > > + See ../clocks/clock-bindings.txt for details. > > +- clock-names: Must include the following entries: > > + - "pcie_ref_125m" > > + - "sata_ref_100m" > > + - "lvds_gate" > > + - "pcie_axi" > > I don't understand why you have completely different clocks here > from the exynos documentation. The clock names should really be > the same. Also, why do you have a "sata_ref_100m" clock? > Is this just driving a device that happens to be on-board > for a specific machine? Same for the "lvds_gate". > Right, we should be able to reuse the clock names. Though I'm not really sure how the Samsung clocks maps to those used on i.MX, as the names are a bit generic. Maybe someone from Samsung could shed a bit of light on this. On i.MX6 the clock names (which I have to agree are pretty bad) map as follows: pcie_axi: host controller main register/bus access clock pcie_ref_125m: pcie phy reference clock sata_ref_100m: pcie bus 100MHz reference clock lvds_gate: bad abstraction. Decides if the reference clock is sourced internal (i.e. the 100MHz ref clock above) or from an SoC external source. We should really find a better way of representing this in the clock tree. Regards, Lucas
On Tuesday 04 March 2014, Lucas Stach wrote: > Right, we should be able to reuse the clock names. Though I'm not really > sure how the Samsung clocks maps to those used on i.MX, as the names are > a bit generic. Maybe someone from Samsung could shed a bit of light on > this. > > On i.MX6 the clock names (which I have to agree are pretty bad) map as > follows: > pcie_axi: host controller main register/bus access clock > pcie_ref_125m: pcie phy reference clock > > sata_ref_100m: pcie bus 100MHz reference clock That doesn't explain why it's called "sata_ref_100m". > lvds_gate: bad abstraction. Decides if the reference clock is sourced > internal (i.e. the 100MHz ref clock above) or from an SoC external > source. We should really find a better way of representing this in the > clock tree. I don't understand this description at all. Can you try to explain that with different words? Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Am Dienstag, den 04.03.2014, 15:53 +0100 schrieb Arnd Bergmann: > On Tuesday 04 March 2014, Lucas Stach wrote: > > Right, we should be able to reuse the clock names. Though I'm not really > > sure how the Samsung clocks maps to those used on i.MX, as the names are > > a bit generic. Maybe someone from Samsung could shed a bit of light on > > this. > > > > On i.MX6 the clock names (which I have to agree are pretty bad) map as > > follows: > > pcie_axi: host controller main register/bus access clock > > pcie_ref_125m: pcie phy reference clock > > > > sata_ref_100m: pcie bus 100MHz reference clock > > That doesn't explain why it's called "sata_ref_100m". > I agree this is bad naming. It's called this way because someone decided to name it like the internal clock it is sourced from on most boards. This really should be pcie_ref, or something. I suspect this corresponds to the pcie_bus clock in the Exynos binding in which case we should just name it this way. > > lvds_gate: bad abstraction. Decides if the reference clock is sourced > > internal (i.e. the 100MHz ref clock above) or from an SoC external > > source. We should really find a better way of representing this in the > > clock tree. > > I don't understand this description at all. Can you try to explain that > with different words? > On i.MX6 the PCIe reference clock is routed through a generic clock pad, which can be configured either as input or output. When the i.MX is the PCI master we source the clock from sata_ref_100m and configure this pad as clock output. Somebody decided to abstract the input/output switch as a gate, which is arguably wrong, this should be a mux deciding between internal or external clock source. The PCIe host driver should really only need the clk pad clock, activation of the sata_ref_100m clock should be handled through parent<->child relationship of those clocks in the clock tree, which isn't properly handled right now. I'll try to fix this up, but it won't be backward compatible in any way. Regards, Lucas
On Tuesday 04 March 2014, Lucas Stach wrote: > > > On i.MX6 the clock names (which I have to agree are pretty bad) map as > > > follows: > > > pcie_axi: host controller main register/bus access clock > > > pcie_ref_125m: pcie phy reference clock > > > > > > sata_ref_100m: pcie bus 100MHz reference clock > > > > That doesn't explain why it's called "sata_ref_100m". > > > I agree this is bad naming. It's called this way because someone decided > to name it like the internal clock it is sourced from on most boards. > This really should be pcie_ref, or something. I suspect this corresponds > to the pcie_bus clock in the Exynos binding in which case we should just > name it this way. Ok, so Exynos is missing one of the other clocks then? Or is the pcie_ref_125m clock something that should actually be listed under the node of the PHY? > > > lvds_gate: bad abstraction. Decides if the reference clock is sourced > > > internal (i.e. the 100MHz ref clock above) or from an SoC external > > > source. We should really find a better way of representing this in the > > > clock tree. > > > > I don't understand this description at all. Can you try to explain that > > with different words? > > > On i.MX6 the PCIe reference clock is routed through a generic clock pad, > which can be configured either as input or output. When the i.MX is the > PCI master we source the clock from sata_ref_100m and configure this pad > as clock output. > Somebody decided to abstract the input/output switch as a gate, which is > arguably wrong, this should be a mux deciding between internal or > external clock source. > > The PCIe host driver should really only need the clk pad clock, > activation of the sata_ref_100m clock should be handled through > parent<->child relationship of those clocks in the clock tree, which > isn't properly handled right now. I'll try to fix this up, but it won't > be backward compatible in any way. Is it possible to treat this clock as a "global" clock rather than a device specific one, and pass NULL as the device for clk_get? That's not nice, but at least it gives you a way to keep it out of the binding, and "just" creates a dependency between the specific PCI host controller and the way that clock is wired up on a particular SoC. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index d6fae13ff062..8274c80fe874 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -1,15 +1,7 @@ * Synopsys Designware PCIe interface Required properties: -- compatible: should contain "snps,dw-pcie" to identify the - core, plus an identifier for the specific instance, such - as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie". -- reg: base addresses and lengths of the pcie controller, - the phy controller, additional register for the phy controller. -- interrupts: interrupt values for level interrupt, - pulse interrupt, special interrupt. -- clocks: from common clock binding: handle to pci clock. -- clock-names: from common clock binding: should be "pcie" and "pcie_bus". +- compatible: should contain "snps,dw-pcie" to identify the core. - #address-cells: set to <3> - #size-cells: set to <2> - device_type: set to "pci" @@ -22,62 +14,3 @@ Required properties: Optional properties: - reset-gpio: gpio pin number of power good signal - -Optional properties for fsl,imx6q-pcie -- power-on-gpio: gpio pin number of power-enable signal -- wake-up-gpio: gpio pin number of incoming wakeup signal -- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal - -Example: - -SoC specific DT Entry: - - pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000 - 0x270000 0x1000 - 0x271000 0x40>; - interrupts = <0 20 0>, <0 21 0>, <0 22 0>; - clocks = <&clock 28>, <&clock 27>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 53>; - num-lanes = <4>; - }; - - pcie@2a0000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x2a0000 0x1000 - 0x272000 0x1000 - 0x271040 0x40>; - interrupts = <0 23 0>, <0 24 0>, <0 25 0>; - clocks = <&clock 29>, <&clock 27>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 56>; - num-lanes = <4>; - }; - -Board specific DT Entry: - - pcie@290000 { - reset-gpio = <&pin_ctrl 5 0>; - }; - - pcie@2a0000 { - reset-gpio = <&pin_ctrl 22 0>; - }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt new file mode 100644 index 000000000000..93fbfd62f13c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -0,0 +1,48 @@ +* Freescale i.MX6 PCIe interface + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: +- compatible: "fsl,imx6q-pcie" +- reg: base addresse and length of the pcie controller +- interrupts: First entry must contain interrupt handle for controller + INTA output. +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "pcie_ref_125m" + - "sata_ref_100m" + - "lvds_gate" + - "pcie_axi" + +Optional properties: +- power-on-gpio: gpio pin number of power-enable signal +- wake-up-gpio: gpio pin number of incoming wakeup signal +- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal + +Example: + + pcie@0x01000000 { + compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; + reg = <0x01ffc000 0x4000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 + 0x81000000 0 0 0x01f80000 0 0x00010000 + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; + num-lanes = <1>; + + interrupts = <0 123 0x04>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; + clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; + }; diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt new file mode 100644 index 000000000000..0b4de1014876 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt @@ -0,0 +1,70 @@ +* Samsung Exynos 5440 PCIe interface + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: +- compatible: "samsung,exynos5440-pcie" +- reg: base addresses and lengths of the pcie controller, + the phy controller, additional register for the phy controller. +- interrupts: A list of interrupt outputs for level interrupt, + pulse interrupt, special interrupt. +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "pcie" + - "pcie_bus" + +Example: + +SoC specific DT Entry: + + pcie@290000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + clocks = <&clock 28>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + num-lanes = <4>; + }; + + pcie@2a0000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + clocks = <&clock 29>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + num-lanes = <4>; + }; + +Board specific DT Entry: + + pcie@290000 { + reset-gpio = <&pin_ctrl 5 0>; + }; + + pcie@2a0000 { + reset-gpio = <&pin_ctrl 22 0>; + };
The glue around the core designware IP is significantly different between the Exynos and i.MX, which is reflected in the DT bindings. Note that this patch doesn't change any bindings, but just alters the documentation to match reality of deployed DTs and kernels. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- .../devicetree/bindings/pci/designware-pcie.txt | 69 +-------------------- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 48 +++++++++++++++ .../bindings/pci/samsung,exynos5440-pcie.txt | 70 ++++++++++++++++++++++ 3 files changed, 119 insertions(+), 68 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt