| Message ID | 1395787705-31061-4-git-send-email-gregory.clement@free-electrons.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On 26/03/2014 12:52, Sebastian Hesselbarth wrote: > On 03/25/2014 11:48 PM, Gregory CLEMENT wrote: >> ll_set_cpu_coherent is always used on the current CPU, so instead of >> passing the CPU id as argument, ll_set_cpu_coherent() can find it by >> itself. >> >> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> >> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> >> --- > [...] >> diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S >> index 1f2bcd4b5424..6cb26b919787 100644 >> --- a/arch/arm/mach-mvebu/coherency_ll.S >> +++ b/arch/arm/mach-mvebu/coherency_ll.S >> @@ -24,9 +24,7 @@ >> #include <asm/cp15.h> >> >> .text >> -/* >> - * r0: HW CPU id >> - */ >> + >> ENTRY(ll_set_cpu_coherent) >> mrc p15, 0, r1, c1, c0, 0 >> tst r1, #CR_M @ Check MMU bit enabled >> @@ -43,9 +41,11 @@ ENTRY(ll_set_cpu_coherent) >> ldr r0, [r0] >> 2: >> /* Create bit by cpu index */ >> - mov r3, #(1 << 24) >> - lsl r1, r3, r1 >> -ARM_BE8(rev r1, r1) >> + mrc 15, 0, r1, cr0, cr0, 5 >> + and r1, r1, #15 >> + mov r2, #(1 << 24) >> + lsl r1, r2, r1 >> + ARM_BE8(rev r1, r1) > > nit: re-indent ARM_BE8 to the beginning of the line? Good catch! Thanks, Gregory > Sebastian >
On 03/25/2014 11:48 PM, Gregory CLEMENT wrote: > ll_set_cpu_coherent is always used on the current CPU, so instead of > passing the CPU id as argument, ll_set_cpu_coherent() can find it by > itself. > > Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- [...] > diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S > index 1f2bcd4b5424..6cb26b919787 100644 > --- a/arch/arm/mach-mvebu/coherency_ll.S > +++ b/arch/arm/mach-mvebu/coherency_ll.S > @@ -24,9 +24,7 @@ > #include <asm/cp15.h> > > .text > -/* > - * r0: HW CPU id > - */ > + > ENTRY(ll_set_cpu_coherent) > mrc p15, 0, r1, c1, c0, 0 > tst r1, #CR_M @ Check MMU bit enabled > @@ -43,9 +41,11 @@ ENTRY(ll_set_cpu_coherent) > ldr r0, [r0] > 2: > /* Create bit by cpu index */ > - mov r3, #(1 << 24) > - lsl r1, r3, r1 > -ARM_BE8(rev r1, r1) > + mrc 15, 0, r1, cr0, cr0, 5 > + and r1, r1, #15 > + mov r2, #(1 << 24) > + lsl r1, r2, r1 > + ARM_BE8(rev r1, r1) nit: re-indent ARM_BE8 to the beginning of the line? Sebastian -- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 88dd507221fc..51010dbbf7e4 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -44,17 +44,17 @@ static struct of_device_id of_coherency_table[] = { }; /* Function defined in coherency_ll.S */ -int ll_set_cpu_coherent(unsigned int hw_cpu_id); +int ll_set_cpu_coherent(void); -int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id) +int set_cpu_coherent(int smp_group_id) { if (!coherency_base) { - pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id); + pr_warn("Can't make current CPU cache coherent.\n"); pr_warn("Coherency fabric is not initialized\n"); return 1; } - return ll_set_cpu_coherent(hw_cpu_id); + return ll_set_cpu_coherent(); } static inline void mvebu_hwcc_sync_io_barrier(void) @@ -140,7 +140,7 @@ int __init coherency_init(void) sync_cache_w(&coherency_phys_base); coherency_base = of_iomap(np, 0); coherency_cpu_base = of_iomap(np, 1); - set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); + set_cpu_coherent(0); of_node_put(np); } diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h index 760226c41353..c7e5df368d98 100644 --- a/arch/arm/mach-mvebu/coherency.h +++ b/arch/arm/mach-mvebu/coherency.h @@ -16,7 +16,7 @@ extern unsigned long coherency_phys_base; -int set_cpu_coherent(unsigned int cpu_id, int smp_group_id); +int set_cpu_coherent(int smp_group_id); int coherency_init(void); #endif /* __MACH_370_XP_COHERENCY_H */ diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index 1f2bcd4b5424..6cb26b919787 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -24,9 +24,7 @@ #include <asm/cp15.h> .text -/* - * r0: HW CPU id - */ + ENTRY(ll_set_cpu_coherent) mrc p15, 0, r1, c1, c0, 0 tst r1, #CR_M @ Check MMU bit enabled @@ -43,9 +41,11 @@ ENTRY(ll_set_cpu_coherent) ldr r0, [r0] 2: /* Create bit by cpu index */ - mov r3, #(1 << 24) - lsl r1, r3, r1 -ARM_BE8(rev r1, r1) + mrc 15, 0, r1, cr0, cr0, 5 + and r1, r1, #15 + mov r2, #(1 << 24) + lsl r1, r2, r1 + ARM_BE8(rev r1, r1) /* Add CPU to SMP group - Atomic */ add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index f30bc8d78871..cf7abe6554f7 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -31,10 +31,6 @@ ENTRY(armada_xp_secondary_startup) ARM_BE8(setend be ) @ go BE8 if entered LE - /* Read CPU id */ - mrc p15, 0, r1, c0, c0, 5 - and r1, r1, #0xF - /* Add CPU to coherency fabric */ bl ll_set_cpu_coherent b secondary_startup diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index a6da03f5b24e..a99d71a747f0 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -102,7 +102,7 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) set_secondary_cpus_clock(); flush_cache_all(); - set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); + set_cpu_coherent(0); /* * In order to boot the secondary CPUs we need to ensure