Message ID | 1396278589-27882-1-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Mon, Mar 31, 2014 at 06:09:49PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We don't do CPU access to GPU contexts so making the GPU access snoop > the CPU caches seems silly, and potentially expensive. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Maybe define a macro to be HAS_L3_CACHE? The root cause is that our singular enum is not flexible enough to account for all platform variations. Otherwise, lgtm. -Chris
On Mon, Mar 31, 2014 at 04:39:37PM +0100, Chris Wilson wrote: > On Mon, Mar 31, 2014 at 06:09:49PM +0300, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > We don't do CPU access to GPU contexts so making the GPU access snoop > > the CPU caches seems silly, and potentially expensive. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Maybe define a macro to be HAS_L3_CACHE? What should I do with such a macro? > > The root cause is that our singular enum is not flexible enough to > account for all platform variations. > > Otherwise, lgtm. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre
On Tue, Apr 01, 2014 at 01:11:02PM +0300, Ville Syrjälä wrote: > On Mon, Mar 31, 2014 at 04:39:37PM +0100, Chris Wilson wrote: > > On Mon, Mar 31, 2014 at 06:09:49PM +0300, ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > We don't do CPU access to GPU contexts so making the GPU access snoop > > > the CPU caches seems silly, and potentially expensive. > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Maybe define a macro to be HAS_L3_CACHE? > > What should I do with such a macro? I am trying to express what exactly we are testing for here. It is not exactly LLC we care about, but L3 to hide the context switch latency. Even though Ben thinks that's a waste of our limited resources. -Chris
On Tue, Apr 01, 2014 at 11:19:19AM +0100, Chris Wilson wrote: > On Tue, Apr 01, 2014 at 01:11:02PM +0300, Ville Syrjälä wrote: > > On Mon, Mar 31, 2014 at 04:39:37PM +0100, Chris Wilson wrote: > > > On Mon, Mar 31, 2014 at 06:09:49PM +0300, ville.syrjala@linux.intel.com wrote: > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > > > We don't do CPU access to GPU contexts so making the GPU access snoop > > > > the CPU caches seems silly, and potentially expensive. > > > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > Maybe define a macro to be HAS_L3_CACHE? > > > > What should I do with such a macro? > > I am trying to express what exactly we are testing for here. It is not > exactly LLC we care about, but L3 to hide the context switch latency. > Even though Ben thinks that's a waste of our limited resources. VLV has L3 too, but we can't control it via the PTEs.
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 6043062..746fb23 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -240,7 +240,7 @@ __create_hw_context(struct drm_device *dev, return ERR_PTR(-ENOMEM); } - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_INFO(dev)->gen >= 7 && HAS_LLC(dev)) { ret = i915_gem_object_set_cache_level(ctx->obj, I915_CACHE_L3_LLC); /* Failure shouldn't ever happen this early */