| Message ID | 1398658225-25873-6-git-send-email-george.cherian@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Apr 28, 2014 at 09:40:24AM +0530, George Cherian wrote: > cpsw_cpts_rft_clk has got the choice of 3 clocksources > -dpll_core_m4_ck > -dpll_core_m5_ck > -dpll_disp_m2_ck > > By default dpll_core_m4_ck is selected, witn this as clock > source the CPTS doesnot work properly. It gives clockcheck errors > while running PTP. > > clockcheck: clock jumped backward or running slower than expected! It is strange that I have never seen this error, since I have often tested linuxptp on a beagle bone white. Can you please explain why this clock doesn't work correctly? > By selecting dpll_core_m5_ck as the clocksource fixes this issue. > In AM335x dpll_core_m5_ck is the default clocksource. The choice of clock source in the CPTS driver originally came from TI. It would be nice to know why that was the wrong choice. Thanks, Richard
On 4/28/2014 12:40 PM, Richard Cochran wrote: > On Mon, Apr 28, 2014 at 09:40:24AM +0530, George Cherian wrote: >> cpsw_cpts_rft_clk has got the choice of 3 clocksources >> -dpll_core_m4_ck >> -dpll_core_m5_ck >> -dpll_disp_m2_ck >> >> By default dpll_core_m4_ck is selected, witn this as clock >> source the CPTS doesnot work properly. It gives clockcheck errors >> while running PTP. >> >> clockcheck: clock jumped backward or running slower than expected! > It is strange that I have never seen this error, since I have often > tested linuxptp on a beagle bone white. In beagle bone white (AM335x) CPTS has a choice of 2 clocksource -dpll_core_m5_ck -dpll_core_m4_ck and by default dpll_core_m5_ck is used. Where as in AM437x the default clocksource used is dpll_core_m4_ck . You can change the clocksource in beagle bone white by writing 1 to 0x44e00520 (By default its 0). > > Can you please explain why this clock doesn't work correctly? > >> By selecting dpll_core_m5_ck as the clocksource fixes this issue. >> In AM335x dpll_core_m5_ck is the default clocksource. > The choice of clock source in the CPTS driver originally came from > TI. It would be nice to know why that was the wrong choice. > > Thanks, > Richard
On Mon, Apr 28, 2014 at 06:25:56PM +0530, George Cherian wrote: > In beagle bone white (AM335x) CPTS has a choice of 2 clocksource > -dpll_core_m5_ck > -dpll_core_m4_ck > and by default dpll_core_m5_ck is used. Where as in AM437x the > default clocksource used is dpll_core_m4_ck . Is your patch changing the default clock for am335x? If yes, it shouldn't. If no, then the patch description should say so. Thanks, Richard
Hi Richard, On 4/28/2014 9:48 PM, Richard Cochran wrote: > On Mon, Apr 28, 2014 at 06:25:56PM +0530, George Cherian wrote: >> In beagle bone white (AM335x) CPTS has a choice of 2 clocksource >> -dpll_core_m5_ck >> -dpll_core_m4_ck >> and by default dpll_core_m5_ck is used. Where as in AM437x the >> default clocksource used is dpll_core_m4_ck . > Is your patch changing the default clock for am335x? No > > If yes, it shouldn't. > If no, then the patch description should say so. I am modifying the file drivers/clk/ti/clk-43xx.c for am33xx its drivers/clk/ti/clk-33xx.c > Thanks, > Richard > >
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 67c8de5..b4877e0 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -110,9 +110,25 @@ static struct ti_dt_clk am43xx_clks[] = { int __init am43xx_dt_clk_init(void) { + struct clk *clk1, *clk2; + ti_dt_clocks_register(am43xx_clks); omap2_clk_disable_autoidle_all(); + /* + * cpsw_cpts_rft_clk has got the choice of 3 clocksources + * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck. + * By default dpll_core_m4_ck is selected, witn this as clock + * source the CPTS doesnot work properly. It gives clockcheck errors + * while running PTP. + * clockcheck: clock jumped backward or running slower than expected! + * By selecting dpll_core_m5_ck as the clocksource fixes this issue. + * In AM335x dpll_core_m5_ck is the default clocksource. + */ + clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); + clk2 = clk_get_sys(NULL, "dpll_core_m5_ck"); + clk_set_parent(clk1, clk2); + return 0; }
cpsw_cpts_rft_clk has got the choice of 3 clocksources -dpll_core_m4_ck -dpll_core_m5_ck -dpll_disp_m2_ck By default dpll_core_m4_ck is selected, witn this as clock source the CPTS doesnot work properly. It gives clockcheck errors while running PTP. clockcheck: clock jumped backward or running slower than expected! By selecting dpll_core_m5_ck as the clocksource fixes this issue. In AM335x dpll_core_m5_ck is the default clocksource. Signed-off-by: George Cherian <george.cherian@ti.com> --- drivers/clk/ti/clk-43xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)