diff mbox

[V2,1/2] ARM: EXYNOS: Update secondary boot addr for secure mode

Message ID 1400557810-28428-1-git-send-email-tushar.behera@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Tushar Behera May 20, 2014, 3:50 a.m. UTC
From: Sachin Kamat <sachin.kamat@linaro.org>

Almost all Exynos-series of SoCs that run in secure mode don't need
additional offset for every CPU, with Exynos4412 being the only
exception.

Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420).

While at it, fix the coding style (space around *).

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
---
Changes for V2:
* Changed the condition statement as per review comment
* Fixed coding style

 arch/arm/mach-exynos/firmware.c |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

Comments

Tushar Behera May 23, 2014, 4:12 a.m. UTC | #1
On 20 May 2014 09:20, Tushar Behera <tushar.behera@linaro.org> wrote:
> From: Sachin Kamat <sachin.kamat@linaro.org>
>
> Almost all Exynos-series of SoCs that run in secure mode don't need
> additional offset for every CPU, with Exynos4412 being the only
> exception.
>
> Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420).
>
> While at it, fix the coding style (space around *).
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
> ---
> Changes for V2:
> * Changed the condition statement as per review comment
> * Fixed coding style
>
>  arch/arm/mach-exynos/firmware.c |    9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>

Kukjin,

Would you please pick this patch and patch 2/2 for this merge window?

[PATCH RESEND 2/2] ARM: dts: Add secure firmware support for Arndale-octa

> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index 739bdc8..7d18103 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -50,8 +50,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>
>         boot_reg = sysram_ns_base_addr + 0x1c;
>
> -       if (!soc_is_exynos4212())
> -               boot_reg += 4*cpu;
> +       /*
> +        * Almost all Exynos-series of SoCs that run in secure mode don't need
> +        * additional offset for every CPU, with Exynos4412 being the only
> +        * exception.
> +        */
> +       if (soc_is_exynos4412())
> +               boot_reg += 4 * cpu;
>
>         __raw_writel(boot_addr, boot_reg);
>         return 0;
> --
> 1.7.9.5
>
Sachin Kamat May 24, 2014, 4:48 a.m. UTC | #2
On 20 May 2014 09:20, Tushar Behera <tushar.behera@linaro.org> wrote:
> From: Sachin Kamat <sachin.kamat@linaro.org>
>
> Almost all Exynos-series of SoCs that run in secure mode don't need
> additional offset for every CPU, with Exynos4412 being the only
> exception.
>
> Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420).
>
> While at it, fix the coding style (space around *).
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
> ---
> Changes for V2:
> * Changed the condition statement as per review comment
> * Fixed coding style
>
>  arch/arm/mach-exynos/firmware.c |    9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index 739bdc8..7d18103 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -50,8 +50,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
>
>         boot_reg = sysram_ns_base_addr + 0x1c;
>
> -       if (!soc_is_exynos4212())
> -               boot_reg += 4*cpu;
> +       /*
> +        * Almost all Exynos-series of SoCs that run in secure mode don't need
> +        * additional offset for every CPU, with Exynos4412 being the only
> +        * exception.
> +        */
> +       if (soc_is_exynos4412())
> +               boot_reg += 4 * cpu;
>
>         __raw_writel(boot_addr, boot_reg);
>         return 0;
> --
> 1.7.9.5
>

 Kukjin,
This series is required for properly booting A15 cores on Arndale octa.
Please apply them.
diff mbox

Patch

diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 739bdc8..7d18103 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -50,8 +50,13 @@  static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 
 	boot_reg = sysram_ns_base_addr + 0x1c;
 
-	if (!soc_is_exynos4212())
-		boot_reg += 4*cpu;
+	/*
+	 * Almost all Exynos-series of SoCs that run in secure mode don't need
+	 * additional offset for every CPU, with Exynos4412 being the only
+	 * exception.
+	 */
+	if (soc_is_exynos4412())
+		boot_reg += 4 * cpu;
 
 	__raw_writel(boot_addr, boot_reg);
 	return 0;