| Message ID | 1400831485-28576-7-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, May 23, 2014 at 03:51:09PM +0800, Chen-Yu Tsai wrote: > The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a > N multiplier factor that starts from 1, not 0. > > This patch adds an option to the clock driver's config data structures > to define the difference. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Maxime
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c index 3806d97..399cf4d 100644 --- a/drivers/clk/sunxi/clk-factors.c +++ b/drivers/clk/sunxi/clk-factors.c @@ -62,7 +62,10 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw, p = FACTOR_GET(config->pshift, config->pwidth, reg); /* Calculate the rate */ - rate = (parent_rate * n * (k + 1) >> p) / (m + 1); + if (config->n_from_one) + rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1); + else + rate = (parent_rate * n * (k + 1) >> p) / (m + 1); return rate; } diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h index 02e1a43..0484a48 100644 --- a/drivers/clk/sunxi/clk-factors.h +++ b/drivers/clk/sunxi/clk-factors.h @@ -15,6 +15,7 @@ struct clk_factors_config { u8 mwidth; u8 pshift; u8 pwidth; + u8 n_from_one; }; struct clk_factors {
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a N multiplier factor that starts from 1, not 0. This patch adds an option to the clock driver's config data structures to define the difference. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi/clk-factors.c | 5 ++++- drivers/clk/sunxi/clk-factors.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-)