Message ID | 1400523003-27082-3-git-send-email-alexandre.belloni@free-electrons.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Mon, May 19, 2014 at 08:10:03PM +0200, Alexandre Belloni wrote: > This is the documentation for the Allwinner Socs PWM bindings. "SoCs". > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt b/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt [...] > +Allwinner PWM controller "Allwinner SoC"? > + > +Required properties: > + - compatible: should be one of: > + - "allwinner,sun4i-a10-pwm" > + - "allwinner,sun7i-a20-pwm" > + - reg: physical base address and length of the controller's registers > + - #pwm-cells: should be 3. See pwm.txt in this directory for a description of > + the cells format. > + - clocks: from common clock binding, handle to the parent clock. This is a sentence, so should start with a capital letter. Thierry
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt b/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt new file mode 100644 index 000000000000..9eda87e7d233 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sunxi.txt @@ -0,0 +1,20 @@ +Allwinner PWM controller + +Required properties: + - compatible: should be one of: + - "allwinner,sun4i-a10-pwm" + - "allwinner,sun7i-a20-pwm" + - reg: physical base address and length of the controller's registers + - #pwm-cells: should be 3. See pwm.txt in this directory for a description of + the cells format. + - clocks: from common clock binding, handle to the parent clock. + +Example: + + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + };