OMAP3: PM: Fix SDRC register addresses

Message ID	1249477918-7200-1-git-send-email-ext-roger.quadros@nokia.com (mailing list archive)
State	Accepted
Delegated to:	Kevin Hilman
Headers	show Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n75DCiZG030953 for <patchwork-omap@patchwork.kernel.org>; Wed, 5 Aug 2009 13:12:44 GMT From: Roger Quadros <ext-roger.quadros@nokia.com> To: khilman@deeprootsystems.com, paul@pwsan.com Cc: linux-omap@vger.kernel.org Subject: [PATCH] OMAP3: PM: Fix SDRC register addresses Date: Wed, 5 Aug 2009 16:11:58 +0300 Message-Id: <1249477918-7200-1-git-send-email-ext-roger.quadros@nokia.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk

Message ID

1249477918-7200-1-git-send-email-ext-roger.quadros@nokia.com (mailing list archive)

State

Accepted

Delegated to:

Kevin Hilman

Headers

From: Roger Quadros <ext-roger.quadros@nokia.com>
To: khilman@deeprootsystems.com, paul@pwsan.com
Cc: linux-omap@vger.kernel.org
Subject: [PATCH] OMAP3: PM: Fix SDRC register addresses
Date: Wed,  5 Aug 2009 16:11:58 +0300
Message-Id: <1249477918-7200-1-git-send-email-ext-roger.quadros@nokia.com>
Sender: linux-omap-owner@vger.kernel.org
Precedence: bulk

Commit Message

Roger Quadros Aug. 5, 2009, 1:11 p.m. UTC

SDRC addresses are offset from OMAP3430_SDRC_RT_BASE and not
OMAP3430_SMS_RT_BASE.
This fixes OFF mode on EMU/HS devices.

Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>
---
 arch/arm/mach-omap2/sleep34xx.S |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

Comments

Kevin Hilman Aug. 5, 2009, 3:10 p.m. UTC | #1

Roger Quadros <ext-roger.quadros@nokia.com> writes:

> SDRC addresses are offset from OMAP3430_SDRC_RT_BASE and not
> OMAP3430_SMS_RT_BASE.
> This fixes OFF mode on EMU/HS devices.
>
> Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>

Indeed, this was a merge goof on my part.  Will fold into
earlier patch to undo.

Thanks,

Kevin

> ---
>  arch/arm/mach-omap2/sleep34xx.S |   14 +++++++-------
>  1 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 807b23e..53b6da9 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -49,13 +49,13 @@
>  #define SCRATCHPAD_BASE_P	(OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
>  						+ SCRATCHPAD_MEM_OFFS)
>  #define SDRC_POWER_V		OMAP34XX_SDRC_REGADDR(SDRC_POWER)
> -#define SDRC_SYSCONFIG_P	(OMAP3430_SMS_RT_BASE + SDRC_SYSCONFIG)
> -#define SDRC_MR_0_P		(OMAP3430_SMS_RT_BASE + SDRC_MR_0)
> -#define SDRC_EMR2_0_P		(OMAP3430_SMS_RT_BASE + SDRC_EMR2_0)
> -#define SDRC_MANUAL_0_P		(OMAP3430_SMS_RT_BASE + SDRC_MANUAL_0)
> -#define SDRC_MR_1_P		(OMAP3430_SMS_RT_BASE + SDRC_MR_1)
> -#define SDRC_EMR2_1_P		(OMAP3430_SMS_RT_BASE + SDRC_EMR2_1)
> -#define SDRC_MANUAL_1_P		(OMAP3430_SMS_RT_BASE + SDRC_MANUAL_1)
> +#define SDRC_SYSCONFIG_P	(OMAP3430_SDRC_RT_BASE + SDRC_SYSCONFIG)
> +#define SDRC_MR_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_MR_0)
> +#define SDRC_EMR2_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_EMR2_0)
> +#define SDRC_MANUAL_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_MANUAL_0)
> +#define SDRC_MR_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_MR_1)
> +#define SDRC_EMR2_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_EMR2_1)
> +#define SDRC_MANUAL_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_MANUAL_1)
>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>  
> -- 
> 1.6.0.4
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Paul Walmsley Aug. 7, 2009, 11:48 a.m. UTC | #2

On Wed, 5 Aug 2009, Roger Quadros wrote:

> SDRC addresses are offset from OMAP3430_SDRC_RT_BASE and not
> OMAP3430_SMS_RT_BASE.
> This fixes OFF mode on EMU/HS devices.
> 
> Signed-off-by: Roger Quadros <ext-roger.quadros@nokia.com>

Signed-off-by: Paul Walmsley <paul@pwsan.com>

> ---
>  arch/arm/mach-omap2/sleep34xx.S |   14 +++++++-------
>  1 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 807b23e..53b6da9 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -49,13 +49,13 @@
>  #define SCRATCHPAD_BASE_P	(OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
>  						+ SCRATCHPAD_MEM_OFFS)
>  #define SDRC_POWER_V		OMAP34XX_SDRC_REGADDR(SDRC_POWER)
> -#define SDRC_SYSCONFIG_P	(OMAP3430_SMS_RT_BASE + SDRC_SYSCONFIG)
> -#define SDRC_MR_0_P		(OMAP3430_SMS_RT_BASE + SDRC_MR_0)
> -#define SDRC_EMR2_0_P		(OMAP3430_SMS_RT_BASE + SDRC_EMR2_0)
> -#define SDRC_MANUAL_0_P		(OMAP3430_SMS_RT_BASE + SDRC_MANUAL_0)
> -#define SDRC_MR_1_P		(OMAP3430_SMS_RT_BASE + SDRC_MR_1)
> -#define SDRC_EMR2_1_P		(OMAP3430_SMS_RT_BASE + SDRC_EMR2_1)
> -#define SDRC_MANUAL_1_P		(OMAP3430_SMS_RT_BASE + SDRC_MANUAL_1)
> +#define SDRC_SYSCONFIG_P	(OMAP3430_SDRC_RT_BASE + SDRC_SYSCONFIG)
> +#define SDRC_MR_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_MR_0)
> +#define SDRC_EMR2_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_EMR2_0)
> +#define SDRC_MANUAL_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_MANUAL_0)
> +#define SDRC_MR_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_MR_1)
> +#define SDRC_EMR2_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_EMR2_1)
> +#define SDRC_MANUAL_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_MANUAL_1)
>  #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
>  #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
>  
> -- 
> 1.6.0.4
> 


- Paul
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diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 807b23e..53b6da9 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -49,13 +49,13 @@ 
 #define SCRATCHPAD_BASE_P	(OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
 						+ SCRATCHPAD_MEM_OFFS)
 #define SDRC_POWER_V		OMAP34XX_SDRC_REGADDR(SDRC_POWER)
-#define SDRC_SYSCONFIG_P	(OMAP3430_SMS_RT_BASE + SDRC_SYSCONFIG)
-#define SDRC_MR_0_P		(OMAP3430_SMS_RT_BASE + SDRC_MR_0)
-#define SDRC_EMR2_0_P		(OMAP3430_SMS_RT_BASE + SDRC_EMR2_0)
-#define SDRC_MANUAL_0_P		(OMAP3430_SMS_RT_BASE + SDRC_MANUAL_0)
-#define SDRC_MR_1_P		(OMAP3430_SMS_RT_BASE + SDRC_MR_1)
-#define SDRC_EMR2_1_P		(OMAP3430_SMS_RT_BASE + SDRC_EMR2_1)
-#define SDRC_MANUAL_1_P		(OMAP3430_SMS_RT_BASE + SDRC_MANUAL_1)
+#define SDRC_SYSCONFIG_P	(OMAP3430_SDRC_RT_BASE + SDRC_SYSCONFIG)
+#define SDRC_MR_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_MR_0)
+#define SDRC_EMR2_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_EMR2_0)
+#define SDRC_MANUAL_0_P		(OMAP3430_SDRC_RT_BASE + SDRC_MANUAL_0)
+#define SDRC_MR_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_MR_1)
+#define SDRC_EMR2_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_EMR2_1)
+#define SDRC_MANUAL_1_P		(OMAP3430_SDRC_RT_BASE + SDRC_MANUAL_1)
 #define SDRC_DLLA_STATUS_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 #define SDRC_DLLA_CTRL_V	OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)

OMAP3: PM: Fix SDRC register addresses

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