diff mbox

[v3,3/7] ARM: dts: Add PPMU device tree support for Exynos5250

Message ID 1405449266-26267-1-git-send-email-a.kesavan@samsung.com (mailing list archive)
State Not Applicable, archived
Headers show

Commit Message

Abhilash Kesavan July 15, 2014, 6:34 p.m. UTC
PPMU is required by the exynos5250 devfreq driver. Add a device
tree node for it.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 .../bindings/arm/exynos/ppmu-exynos5.txt           |   26 ++++++++++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi                  |    8 ++++++
 2 files changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt

Comments

Tomasz Figa July 16, 2014, 10:55 a.m. UTC | #1
Hi Abhilash,

Please see my comments inline. Also CCing some DT maintainers.

On 15.07.2014 20:34, Abhilash Kesavan wrote:
> PPMU is required by the exynos5250 devfreq driver. Add a device
> tree node for it.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  .../bindings/arm/exynos/ppmu-exynos5.txt           |   26 ++++++++++++++++++++
>  arch/arm/boot/dts/exynos5250.dtsi                  |    8 ++++++
>  2 files changed, 34 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
> new file mode 100644
> index 0000000..a6a2eba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
> @@ -0,0 +1,26 @@
> +Exynos PPMU driver
> +-------------------
> +
> +Performance events are primitive values used to get performance data. These
> +events provide information about the behavior of the SoC that can be used
> +when analyzing system performance. These events are made visible using the
> +PPMU logic.
> +Exynos PPMU driver is used by the exynos5 devfreq drivers to control the
> +bus frequency/voltage.
> +
> +Required properties:
> +- compatible: "samsung,exynos5250-int-busfreq", "samsung,exynos5420-int-busfreq"

If this is a binding for PPMU, shouldn't the compatible string contain
the "ppmu" string too? E.g. "samsung,exynos5250-ppmu",
"samsung,exynos5420-ppmu".

> +- reg:
> +	* physical base address of the PPMUs (e.g DDR, Right Bus, Left bus etc)
> +	and length of memory mapped region.

Since PPMU are separate IP blocks, they should have their own device
nodes with only address ranges of their own. Representing all PPMUs in
the SoC with a single node is incorrect.

Best regards,
Tomasz
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Tomasz Figa July 16, 2014, 10:56 a.m. UTC | #2
Actually one more comment.

On 15.07.2014 20:34, Abhilash Kesavan wrote:

[snip]

> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 834fb5a..5284f00 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -778,4 +778,12 @@
>  		clocks = <&clock CLK_SSS>;
>  		clock-names = "secss";
>  	};
> +
> +	ppmu@10C40000 {
> +		compatible = "samsung,exynos5250-int-busfreq";
> +		reg = <0x10C40000 0x2000	/* PPMU_DDR_C */
> +		       0x10C50000 0x2000	/* PPMU_DDR_L */
> +		       0x10CB0000 0x2000	/* PPMU_DDR_R */
> +		       0x13660000 0x2000>;	/* PPMU_RIGHT */
> +	};
>  };
> 

Please separate patches adding the binding from patches modifying device
tree sources. Those are two logically separate changes.

Best regards,
Tomasz
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Abhilash Kesavan July 16, 2014, 6 p.m. UTC | #3
Hi Tomasz,

On Wed, Jul 16, 2014 at 4:25 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Abhilash,
>
> Please see my comments inline. Also CCing some DT maintainers.
>
> On 15.07.2014 20:34, Abhilash Kesavan wrote:
>> PPMU is required by the exynos5250 devfreq driver. Add a device
>> tree node for it.
>>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  .../bindings/arm/exynos/ppmu-exynos5.txt           |   26 ++++++++++++++++++++
>>  arch/arm/boot/dts/exynos5250.dtsi                  |    8 ++++++
>>  2 files changed, 34 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
>> new file mode 100644
>> index 0000000..a6a2eba
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
>> @@ -0,0 +1,26 @@
>> +Exynos PPMU driver
>> +-------------------
>> +
>> +Performance events are primitive values used to get performance data. These
>> +events provide information about the behavior of the SoC that can be used
>> +when analyzing system performance. These events are made visible using the
>> +PPMU logic.
>> +Exynos PPMU driver is used by the exynos5 devfreq drivers to control the
>> +bus frequency/voltage.
>> +
>> +Required properties:
>> +- compatible: "samsung,exynos5250-int-busfreq", "samsung,exynos5420-int-busfreq"
>
> If this is a binding for PPMU, shouldn't the compatible string contain
> the "ppmu" string too? E.g. "samsung,exynos5250-ppmu",
> "samsung,exynos5420-ppmu".
>
>> +- reg:
>> +     * physical base address of the PPMUs (e.g DDR, Right Bus, Left bus etc)
>> +     and length of memory mapped region.
>
> Since PPMU are separate IP blocks, they should have their own device
> nodes with only address ranges of their own. Representing all PPMUs in
> the SoC with a single node is incorrect.
OK, I will re-work this.
>
> Best regards,
> Tomasz
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Abhilash Kesavan July 16, 2014, 6:01 p.m. UTC | #4
Hi Tomasz,

On Wed, Jul 16, 2014 at 4:26 PM, Tomasz Figa <t.figa@samsung.com> wrote:
> Actually one more comment.
>
> On 15.07.2014 20:34, Abhilash Kesavan wrote:
>
> [snip]
>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
>> index 834fb5a..5284f00 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -778,4 +778,12 @@
>>               clocks = <&clock CLK_SSS>;
>>               clock-names = "secss";
>>       };
>> +
>> +     ppmu@10C40000 {
>> +             compatible = "samsung,exynos5250-int-busfreq";
>> +             reg = <0x10C40000 0x2000        /* PPMU_DDR_C */
>> +                    0x10C50000 0x2000        /* PPMU_DDR_L */
>> +                    0x10CB0000 0x2000        /* PPMU_DDR_R */
>> +                    0x13660000 0x2000>;      /* PPMU_RIGHT */
>> +     };
>>  };
>>
>
> Please separate patches adding the binding from patches modifying device
> tree sources. Those are two logically separate changes.
Will split them in the next version.
>
> Best regards,
> Tomasz
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
new file mode 100644
index 0000000..a6a2eba
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
@@ -0,0 +1,26 @@ 
+Exynos PPMU driver
+-------------------
+
+Performance events are primitive values used to get performance data. These
+events provide information about the behavior of the SoC that can be used
+when analyzing system performance. These events are made visible using the
+PPMU logic.
+Exynos PPMU driver is used by the exynos5 devfreq drivers to control the
+bus frequency/voltage.
+
+Required properties:
+- compatible: "samsung,exynos5250-int-busfreq", "samsung,exynos5420-int-busfreq"
+- reg:
+	* physical base address of the PPMUs (e.g DDR, Right Bus, Left bus etc)
+	and length of memory mapped region.
+
+Example:
+--------
+
+	ppmu@0x10C40000 {
+		compatible = "samsung,exynos5250-int-busfreq";
+		reg = <0x10C40000 0x2000
+		       0x10C50000 0x2000
+		       0x10CB0000 0x2000
+		       0x13660000 0x2000>;
+	};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..5284f00 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -778,4 +778,12 @@ 
 		clocks = <&clock CLK_SSS>;
 		clock-names = "secss";
 	};
+
+	ppmu@10C40000 {
+		compatible = "samsung,exynos5250-int-busfreq";
+		reg = <0x10C40000 0x2000	/* PPMU_DDR_C */
+		       0x10C50000 0x2000	/* PPMU_DDR_L */
+		       0x10CB0000 0x2000	/* PPMU_DDR_R */
+		       0x13660000 0x2000>;	/* PPMU_RIGHT */
+	};
 };