| Message ID | 1406243908-1123-10-git-send-email-keithp@keithp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Keith Packard <keithp@keithp.com> writes: > Make sure the pitch and tiling are correct. > Make sure there's a BO we can get at. I thought we couldn't change these parameters, but now I can't find what prevents them from changing. Can you cite sources?
Eric Anholt <eric@anholt.net> writes: > Keith Packard <keithp@keithp.com> writes: > >> Make sure the pitch and tiling are correct. >> Make sure there's a BO we can get at. > > I thought we couldn't change these parameters, but now I can't find what > prevents them from changing. Can you cite sources? Looks like we *can* change tiling format. That actually makes me kinda happy as that explains why we were able to allocate a linear frame buffer for the X front buffer (due to a bug) and page flip to DRI3 buffers which are always tiled. However, we can't change the pitch. From the kernel driver: /* * TILEOFF/LINOFF registers can't be changed via MI display flips. * Note that pitch changes could also affect these register. */ if (INTEL_INFO(dev)->gen > 3 && (fb->offsets[0] != crtc->primary->fb->offsets[0] || fb->pitches[0] != crtc->primary->fb->pitches[0])) return -EINVAL; I'll remove the tiling check.
On Wed, Jul 30, 2014 at 11:01:48PM -0700, Keith Packard wrote: > Eric Anholt <eric@anholt.net> writes: > > > Keith Packard <keithp@keithp.com> writes: > > > >> Make sure the pitch and tiling are correct. > >> Make sure there's a BO we can get at. > > > > I thought we couldn't change these parameters, but now I can't find what > > prevents them from changing. Can you cite sources? > > Looks like we *can* change tiling format. That actually makes me kinda > happy as that explains why we were able to allocate a linear frame > buffer for the X front buffer (due to a bug) and page flip to DRI3 > buffers which are always tiled. > > However, we can't change the pitch. From the kernel driver: > > /* > * TILEOFF/LINOFF registers can't be changed via MI display flips. > * Note that pitch changes could also affect these register. > */ > if (INTEL_INFO(dev)->gen > 3 && > (fb->offsets[0] != crtc->primary->fb->offsets[0] || > fb->pitches[0] != crtc->primary->fb->pitches[0])) > return -EINVAL; > > I'll remove the tiling check. Now that we have mmio flips in the kernel we can start to relax that restriction. That still needs a bit more work in the mmio flip code but I believe some people working on just that. We could even change the pixel format, except a check was added to drm_mode_page_flip_ioctl() to prevent that, so I guess it was deemed that the API isn't meant to allow that.
Ville Syrjälä <ville.syrjala@linux.intel.com> writes: > Now that we have mmio flips in the kernel we can start to relax that > restriction. That still needs a bit more work in the mmio flip code > but I believe some people working on just that. I couldn't find any tiling restrictions in the current (ring-based) flip code; did I just miss them? > We could even change the pixel format, except a check was added to > drm_mode_page_flip_ioctl() to prevent that, so I guess it was > deemed that the API isn't meant to allow that. Yeah, not sure I care about this; 32bpp is pretty much the only format I want.
On Thu, Jul 31, 2014 at 08:20:20AM -0700, Keith Packard wrote: > Ville Syrjälä <ville.syrjala@linux.intel.com> writes: > > > Now that we have mmio flips in the kernel we can start to relax that > > restriction. That still needs a bit more work in the mmio flip code > > but I believe some people working on just that. > > I couldn't find any tiling restrictions in the current (ring-based) flip > code; did I just miss them? No, changing tiling is supposed to work via cs flips. Except it doesn't actually work on VLV for some reason. We now fall back to mmio flip on VLV for that, so given a recent enough kernel it should just work (tm) on all platforms. I was referring to the relaxing the restrictions on stride changes. > > > We could even change the pixel format, except a check was added to > > drm_mode_page_flip_ioctl() to prevent that, so I guess it was > > deemed that the API isn't meant to allow that. > > Yeah, not sure I care about this; 32bpp is pretty much the only format I > want. You just need to be careful with the X vs. A because the kernel considers those distinct pixel formats. I now regret adding that distinciton to the pixel formats, but sadly I don't own a time machine so I can't undo it.
diff --git a/src/uxa/intel_present.c b/src/uxa/intel_present.c index c53d71d..b901fb1 100644 --- a/src/uxa/intel_present.c +++ b/src/uxa/intel_present.c @@ -248,6 +248,8 @@ intel_present_check_flip(RRCrtcPtr crtc, ScreenPtr screen = window->drawable.pScreen; ScrnInfoPtr scrn = xf86ScreenToScrn(screen); intel_screen_private *intel = intel_get_screen_private(scrn); + dri_bo *bo; + uint32_t tiling, swizzle; if (!scrn->vtSema) return FALSE; @@ -261,6 +263,22 @@ intel_present_check_flip(RRCrtcPtr crtc, if (crtc && !intel_crtc_on(crtc->devPrivate)) return FALSE; + /* Check stride, can't change that on flip */ + if (pixmap->devKind != intel->front_pitch) + return FALSE; + + /* Make sure there's a bo we can get to */ + bo = intel_get_pixmap_bo(pixmap); + if (!bo) + return FALSE; + + /* Check tiling, can't change that on flip */ + if (drm_intel_bo_get_tiling((drm_intel_bo *) bo, &tiling, &swizzle) != 0) + return FALSE; + + if (tiling != intel->front_tiling) + return FALSE; + return TRUE; }
Make sure the pitch and tiling are correct. Make sure there's a BO we can get at. Signed-off-by: Keith Packard <keithp@keithp.com> --- src/uxa/intel_present.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)