From patchwork Wed Oct 31 09:30:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 10662311 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE88E13BF for ; Wed, 31 Oct 2018 09:30:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC1C22A33E for ; Wed, 31 Oct 2018 09:30:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A05C02A345; Wed, 31 Oct 2018 09:30:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 369D02A33E for ; Wed, 31 Oct 2018 09:30:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727655AbeJaS2J (ORCPT ); Wed, 31 Oct 2018 14:28:09 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:45738 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727527AbeJaS2J (ORCPT ); Wed, 31 Oct 2018 14:28:09 -0400 Received: by mail-wr1-f67.google.com with SMTP id n5-v6so15610302wrw.12 for ; Wed, 31 Oct 2018 02:30:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=i4hHSGsmWMk6v8HT5bX88V/ev/elSNXdtghM/lZz0Hw=; b=ZCz3p/z2iHtuFqhtgamPJy1ulsidAsb59E3JNxE9+0WQI4gv/9r/qXMVaMrIGt+ca5 fqpSqSCoouzTl1oVvuPjPRCl/mz9hZ/MCBvUyvAIyHZxHPBcbe4L7wXNGm16J/yU1fVK hf3h/QR7uGUWjmgCZ+tfFP+NuvKkVgm5y+x94= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=i4hHSGsmWMk6v8HT5bX88V/ev/elSNXdtghM/lZz0Hw=; b=O4minxxT8H0rXoT8595q4MeizVU0AFDJLyKij0Rm1haIUuQEMw1RCP8ro72Z2UwH87 AIkNg297gtJHHrMBZwYF5SBn2zHOLUishJNiGiLTYCoGJ8nEpyQjafRwhu25Cb0pK2nn 9s4hv2EL/Vn1CbhJoCOkpjsdTh87HGHmwL4RpkbHd2Nb707dMljr7oQfR1/A+hbBNF+o VV/lzH5/F2klHXX8LIJn+/wkGk2psMF86NK/OQs+m0O3Age4+MVDynqO7xRHZ9ku3vuE /uvDSceO6/dd4Ik6dUXxu9kjkq2LaCIYSBVSvMobpgNY1qGq2ZYNCf17zVXleyfN+94W OJMA== X-Gm-Message-State: AGRZ1gKGnn82lxF5jkFcwRLGRrtnQmT1TFKq75f+hbPsJovUWezTKcDA eLHqgZen9xr+PmDP5X2fR7Wk8Q== X-Google-Smtp-Source: AJdET5djPhbr+P5/E3mygRyq6IGpWVMkxCxV6Sp6TZ52UqMmR2wV5fg5nPmjb+ZzSjh7K6GnojHwAA== X-Received: by 2002:a5d:4406:: with SMTP id z6-v6mr2046516wrq.294.1540978248230; Wed, 31 Oct 2018 02:30:48 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1086:999:fd1b:8629:a7fc:68b]) by smtp.gmail.com with ESMTPSA id w14-v6sm10737377wrt.73.2018.10.31.02.30.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Oct 2018 02:30:47 -0700 (PDT) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH 0/5] Add support of STM32 hwspinlock Date: Wed, 31 Oct 2018 10:30:27 +0100 Message-Id: <20181031093032.20386-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This serie adds the support of the hardware semaphore block for stm32mp1 SoC. The last patch isn't related to the hardware itself but propose a way to test hwspinlocks. Benjamin Gaignard (5): dt-bindings: hwlock: Document STM32 hwspinlock bindings hwspinlock: add STM32 hwspinlock device ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC ARM: dts: stm32: enable hwspinlock on stm32mp157c-ed1 hwspinlock: Add test module .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 + arch/arm/boot/dts/stm32mp157c.dtsi | 9 ++ drivers/hwspinlock/Kconfig | 18 +++ drivers/hwspinlock/Makefile | 2 + drivers/hwspinlock/hwspinlock_test.c | 132 ++++++++++++++++++ drivers/hwspinlock/stm32_hwspinlock.c | 147 +++++++++++++++++++++ 7 files changed, 335 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt create mode 100644 drivers/hwspinlock/hwspinlock_test.c create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c