[v6,0/4] Forward Error Correction
mbox series

Message ID 20181105233150.1972-1-anusha.srivatsa@intel.com
Headers show
  • Forward Error Correction
Related show


Anusha Srivatsa Nov. 5, 2018, 11:31 p.m. UTC
With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of bit errors in the compressed

v2: Avoid doing aux channel read everytime we check
for FEC support. Instead cache the value of the DPCD
registers, similar to the DSC implementaion (Jani)

v3: Add fec as a state to crtc. Move around the code. (Ville)

v4: s/can_fec/fec_enable; s/intel_dp_can_fec/intel_dp_supports_fec;
Add intel_dp_source supports_fec() (Ville)

v5: Reduce unwanted checks. Pass intel_encoder to fec func
instead of intel_dp. Move code around to suitable place.

v6: Remove warning. rebase.

Rebased on top of: https://patchwork.freedesktop.org/series/51986/ 

Anusha Srivatsa (4):
  i915/dp/fec: Add fec_enable to the crtc state.
  drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
  i915/dp/fec: Configure the Forward Error Correction bits.
  drm/i915/fec: Disable FEC state.

 drivers/gpu/drm/i915/i915_reg.h  |  2 +
 drivers/gpu/drm/i915/intel_ddi.c | 68 ++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_dp.c  | 28 +++++++++++--
 drivers/gpu/drm/i915/intel_drv.h |  3 ++
 4 files changed, 94 insertions(+), 7 deletions(-)