[v13,0/5] Add i.MX8MQ clock driver
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Message ID 1542125975-8448-1-git-send-email-abel.vesa@nxp.com
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  • Add i.MX8MQ clock driver
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Abel Vesa Nov. 13, 2018, 4:19 p.m. UTC
Here is a link to the 12th version:
https://lkml.org/lkml/2018/11/7/642

Changes since v12:
 * replaced the division in clk_pll_recalc_rate in clk-frac
   with do_div as suggested by Stephen

Abel Vesa (2):
  clk: imx: Add imx composite clock
  clk: imx: Add clock driver for i.MX8MQ CCM

Lucas Stach (3):
  dt-bindings: add binding for i.MX8MQ CCM
  clk: imx: add fractional PLL output clock
  clk: imx: Add SCCG PLL type

 .../devicetree/bindings/clock/imx8mq-clock.txt     |  20 +
 drivers/clk/imx/Makefile                           |   6 +-
 drivers/clk/imx/clk-composite-8m.c                 | 178 +++++++
 drivers/clk/imx/clk-frac-pll.c                     | 221 ++++++++
 drivers/clk/imx/clk-imx8mq.c                       | 589 +++++++++++++++++++++
 drivers/clk/imx/clk-sccg-pll.c                     | 256 +++++++++
 drivers/clk/imx/clk.h                              |  64 +++
 include/dt-bindings/clock/imx8mq-clock.h           | 395 ++++++++++++++
 8 files changed, 1728 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx8mq-clock.txt
 create mode 100644 drivers/clk/imx/clk-composite-8m.c
 create mode 100644 drivers/clk/imx/clk-frac-pll.c
 create mode 100644 drivers/clk/imx/clk-imx8mq.c
 create mode 100644 drivers/clk/imx/clk-sccg-pll.c
 create mode 100644 include/dt-bindings/clock/imx8mq-clock.h

Comments

Stephen Boyd Nov. 29, 2018, 12:41 a.m. UTC | #1
Quoting Abel Vesa (2018-11-13 08:19:56)
> Here is a link to the 12th version:
> https://lkml.org/lkml/2018/11/7/642
> 
> Changes since v12:
>  * replaced the division in clk_pll_recalc_rate in clk-frac
>    with do_div as suggested by Stephen
> 
> Abel Vesa (2):
>   clk: imx: Add imx composite clock
>   clk: imx: Add clock driver for i.MX8MQ CCM
> 
> Lucas Stach (3):
>   dt-bindings: add binding for i.MX8MQ CCM
>   clk: imx: add fractional PLL output clock
>   clk: imx: Add SCCG PLL type
> 

I had to apply this set of fixes to silence sparse and smatch warnings
about things that are not right. Please take a look over things and see
if it's sane.

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index bcd31d889584..6d9d3714b4df 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -127,8 +127,8 @@ struct clk *imx8m_clk_composite_flags(const char *name,
 					int num_parents, void __iomem *reg,
 					unsigned long flags)
 {
-	struct clk_hw *hw = NULL, *mux_hw = NULL;
-	struct clk_hw *div_hw = NULL, *gate_hw = NULL;
+	struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
+	struct clk_hw *div_hw, *gate_hw;
 	struct clk_divider *div = NULL;
 	struct clk_gate *gate = NULL;
 	struct clk_mux *mux = NULL;
diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
index a3732be5ad7f..98726206f3c4 100644
--- a/drivers/clk/imx/clk-frac-pll.c
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -14,6 +14,8 @@
 #include <linux/slab.h>
 #include <linux/bitfield.h>
 
+#include "clk.h"
+
 #define PLL_CFG0		0x0
 #define PLL_CFG1		0x4
 
@@ -214,7 +216,7 @@ struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
 	ret = clk_hw_register(NULL, hw);
 	if (ret) {
 		kfree(pll);
-		return ERR_CAST(hw);
+		return ERR_PTR(ret);
 	}
 
 	return hw->clk;
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 4666b96bdb3f..ee7752bace89 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -249,7 +249,7 @@ struct clk *imx_clk_sccg_pll(const char *name,
 	ret = clk_hw_register(NULL, hw);
 	if (ret) {
 		kfree(pll);
-		return ERR_CAST(hw);
+		return ERR_PTR(ret);
 	}
 
 	return hw->clk;
Aisheng Dong Nov. 29, 2018, 7:46 a.m. UTC | #2
> -----Original Message-----
> From: Stephen Boyd [mailto:sboyd@kernel.org]
[...]
> >
> > Changes since v12:
> >  * replaced the division in clk_pll_recalc_rate in clk-frac
> >    with do_div as suggested by Stephen
> >
> > Abel Vesa (2):
> >   clk: imx: Add imx composite clock
> >   clk: imx: Add clock driver for i.MX8MQ CCM
> >
> > Lucas Stach (3):
> >   dt-bindings: add binding for i.MX8MQ CCM
> >   clk: imx: add fractional PLL output clock
> >   clk: imx: Add SCCG PLL type
> >
> 
> I had to apply this set of fixes to silence sparse and smatch warnings about
> things that are not right. Please take a look over things and see if it's sane.
> 

The change looks good to me and tested ok.
I did not see this patch series in your tree.
Do you want us to apply your changes and re-send for easy pick up?

Regards
Dong Aisheng

> diff --git a/drivers/clk/imx/clk-composite-8m.c
> b/drivers/clk/imx/clk-composite-8m.c
> index bcd31d889584..6d9d3714b4df 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -127,8 +127,8 @@ struct clk *imx8m_clk_composite_flags(const char
> *name,
>  					int num_parents, void __iomem *reg,
>  					unsigned long flags)
>  {
> -	struct clk_hw *hw = NULL, *mux_hw = NULL;
> -	struct clk_hw *div_hw = NULL, *gate_hw = NULL;
> +	struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
> +	struct clk_hw *div_hw, *gate_hw;
>  	struct clk_divider *div = NULL;
>  	struct clk_gate *gate = NULL;
>  	struct clk_mux *mux = NULL;
> diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c index
> a3732be5ad7f..98726206f3c4 100644
> --- a/drivers/clk/imx/clk-frac-pll.c
> +++ b/drivers/clk/imx/clk-frac-pll.c
> @@ -14,6 +14,8 @@
>  #include <linux/slab.h>
>  #include <linux/bitfield.h>
> 
> +#include "clk.h"
> +
>  #define PLL_CFG0		0x0
>  #define PLL_CFG1		0x4
> 
> @@ -214,7 +216,7 @@ struct clk *imx_clk_frac_pll(const char *name, const
> char *parent_name,
>  	ret = clk_hw_register(NULL, hw);
>  	if (ret) {
>  		kfree(pll);
> -		return ERR_CAST(hw);
> +		return ERR_PTR(ret);
>  	}
> 
>  	return hw->clk;
> diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c index
> 4666b96bdb3f..ee7752bace89 100644
> --- a/drivers/clk/imx/clk-sccg-pll.c
> +++ b/drivers/clk/imx/clk-sccg-pll.c
> @@ -249,7 +249,7 @@ struct clk *imx_clk_sccg_pll(const char *name,
>  	ret = clk_hw_register(NULL, hw);
>  	if (ret) {
>  		kfree(pll);
> -		return ERR_CAST(hw);
> +		return ERR_PTR(ret);
>  	}
> 
>  	return hw->clk;
Stephen Boyd Nov. 29, 2018, 9:51 p.m. UTC | #3
Quoting Aisheng DONG (2018-11-28 23:46:41)
> > -----Original Message-----
> > From: Stephen Boyd [mailto:sboyd@kernel.org]
> [...]
> > >
> > > Changes since v12:
> > >  * replaced the division in clk_pll_recalc_rate in clk-frac
> > >    with do_div as suggested by Stephen
> > >
> > > Abel Vesa (2):
> > >   clk: imx: Add imx composite clock
> > >   clk: imx: Add clock driver for i.MX8MQ CCM
> > >
> > > Lucas Stach (3):
> > >   dt-bindings: add binding for i.MX8MQ CCM
> > >   clk: imx: add fractional PLL output clock
> > >   clk: imx: Add SCCG PLL type
> > >
> > 
> > I had to apply this set of fixes to silence sparse and smatch warnings about
> > things that are not right. Please take a look over things and see if it's sane.
> > 
> 
> The change looks good to me and tested ok.
> I did not see this patch series in your tree.
> Do you want us to apply your changes and re-send for easy pick up?
> 

I applied this version and my fixes. I'll just mark v14 as superseded.
Thanks for testing!
Shawn Guo Dec. 11, 2018, 8:02 a.m. UTC | #4
On Thu, Nov 29, 2018 at 01:51:04PM -0800, Stephen Boyd wrote:
> Quoting Aisheng DONG (2018-11-28 23:46:41)
> > > -----Original Message-----
> > > From: Stephen Boyd [mailto:sboyd@kernel.org]
> > [...]
> > > >
> > > > Changes since v12:
> > > >  * replaced the division in clk_pll_recalc_rate in clk-frac
> > > >    with do_div as suggested by Stephen
> > > >
> > > > Abel Vesa (2):
> > > >   clk: imx: Add imx composite clock
> > > >   clk: imx: Add clock driver for i.MX8MQ CCM
> > > >
> > > > Lucas Stach (3):
> > > >   dt-bindings: add binding for i.MX8MQ CCM
> > > >   clk: imx: add fractional PLL output clock
> > > >   clk: imx: Add SCCG PLL type
> > > >
> > > 
> > > I had to apply this set of fixes to silence sparse and smatch warnings about
> > > things that are not right. Please take a look over things and see if it's sane.
> > > 
> > 
> > The change looks good to me and tested ok.
> > I did not see this patch series in your tree.
> > Do you want us to apply your changes and re-send for easy pick up?
> > 
> 
> I applied this version and my fixes. I'll just mark v14 as superseded.
> Thanks for testing!

Hi Stephen,

For the same reason as clk-imx7ulp, please keep branch clk-imx8mq
stable.  Thanks.

Shawn