[v5,00/15] Add support for Hygon Dhyana Family 18h processor
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Message ID cover.1554382869.git.puwen@hygon.cn
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  • Add support for Hygon Dhyana Family 18h processor
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Pu Wen April 4, 2019, 1:44 p.m. UTC
As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon)
is a joint venture between AMD and Haiguang Information Technology Co.,
Ltd., aims at providing high performance x86 processors for China
server market.

The first generation Hygon processor(Dhyana) originates from AMD
technology and shares most of the architecture with AMD's family 17h,
but with different CPU vendor ID("HygonGenuine") and family series
number 18h (Hygon negotiated with AMD to make sure that only Hygon
will use family 18h).

To enable support of Xen to Hygon Dhyana CPU, add a new vendor type
(X86_VENDOR_HYGON, with value of 5), and share most of the code with
AMD family 17h.

The MSRs and CPUIDs which are used by this patch series are all defined
in this PPR[1].

This patch series have been applied and tested successfully on Hygon
Dhyana processor, also been tested on AMD EPYC (family 17h) processor.
It works fine and makes no harm to the existing code.

Reference:
[1] https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf


v4->v5:
  - Rebased over https://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=0763cd26
    to fit the new x86 vendor lookup mechanism.
  - Rework patch 15/15 to fit the new x86 vendor lookup mechanism.
  - Add Acked-by from Jan Beulich for patch 02/15 and 04/15.
  - Retain more conditionals from amd.c.
  - Refine coding style.

v3->v4:
  - Revert opt_cpuid_mask_l7s0_(eax/ebx) to amd.c.
  - Create a separate patch to fix common cpuid faulting probing issue
    for AMD and Hygon.
  - Rename _vpmu_init() to common_init() and move the default case into it.
  - Coding style refine.

v2->v3:
  - Rebased on 4.13-unstable and tested against it.
  - Simplify code of hygon.c by re-using early_init_amd().
  - Return false in the function probe_cpuid_faulting().
  - Adjust code for calculating phys_proc_id for Hygon.
  - Abstract common function _vpmu_init() and add hygon_vpmu_init().
  - Refine some comments and descriptions.
  - Add Acked-by from Jan Beulich for x86/cpu/mtrr, x86/cpu/mce,
    x86/spec_ctrl, x86/apic, x86/acpi, x86/iommu, x86/pv, x86/domain,
    x86/domctl and x86/cpuid.

v1->v2:
  - Rebased on 4.12.0-rc3 and tested against it.
  - Move opt_cpuid_mask_l7s0_(eax/ebx) to common.c.
  - Insert Hygon cases after AMD ones instead of above.
  - Remove (rd/wr)msr_hygon_safe and use (rd/wr)msr_safe instead.
  - Remove wrmsr_hygon and use wrmsrl instead.
  - Remove the unnecessary change to xstate.
  - Refine some codes and comments.
  - Add Acked-by from Jan Beulich for x86/traps.
  - Add Acked-by from Wei Liu for tools/libxc.


Pu Wen (15):
  x86/cpu: Create Hygon Dhyana architecture support file
  x86/cpu: Fix common cpuid faulting probing for AMD and Hygon
  x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2
  x86/cpu/vpmu: Add Hygon Dhyana and AMD Zen support for vPMU
  x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure
  x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery
  x86/apic: Add Hygon Dhyana support
  x86/acpi: Add Hygon Dhyana support
  x86/iommu: Add Hygon Dhyana support
  x86/pv: Add Hygon Dhyana support to emulate MSRs access
  x86/domain: Add Hygon Dhyana support
  x86/domctl: Add Hygon Dhyana support
  x86/traps: Add Hygon Dhyana support
  x86/cpuid: Add Hygon Dhyana support
  tools/libxc: Add Hygon Dhyana support

 tools/libxc/xc_cpuid_x86.c             |  11 ++--
 xen/arch/x86/acpi/cpu_idle.c           |   3 +-
 xen/arch/x86/acpi/cpufreq/cpufreq.c    |   8 ++-
 xen/arch/x86/acpi/cpufreq/powernow.c   |   3 +-
 xen/arch/x86/apic.c                    |   5 ++
 xen/arch/x86/cpu/Makefile              |   1 +
 xen/arch/x86/cpu/amd.c                 |   2 +-
 xen/arch/x86/cpu/common.c              |   9 ++-
 xen/arch/x86/cpu/cpu.h                 |   3 +
 xen/arch/x86/cpu/hygon.c               | 114 +++++++++++++++++++++++++++++++++
 xen/arch/x86/cpu/mcheck/amd_nonfatal.c |   5 +-
 xen/arch/x86/cpu/mcheck/mce.c          |   6 +-
 xen/arch/x86/cpu/mcheck/mce_amd.c      |   5 +-
 xen/arch/x86/cpu/mcheck/non-fatal.c    |   3 +-
 xen/arch/x86/cpu/mcheck/vmce.c         |   2 +
 xen/arch/x86/cpu/mtrr/generic.c        |   5 +-
 xen/arch/x86/cpu/vpmu.c                |   8 +++
 xen/arch/x86/cpu/vpmu_amd.c            |  61 ++++++++++++------
 xen/arch/x86/cpuid.c                   |  10 ++-
 xen/arch/x86/dom0_build.c              |   3 +-
 xen/arch/x86/domain.c                  |   9 +--
 xen/arch/x86/domctl.c                  |  13 +++-
 xen/arch/x86/pv/emul-priv-op.c         |  19 ++++--
 xen/arch/x86/spec_ctrl.c               |   6 +-
 xen/arch/x86/traps.c                   |   3 +
 xen/include/asm-x86/iommu.h            |   1 +
 xen/include/asm-x86/vpmu.h             |   1 +
 xen/include/asm-x86/x86-vendors.h      |   7 +-
 xen/lib/x86/cpuid.c                    |   6 ++
 29 files changed, 275 insertions(+), 57 deletions(-)
 create mode 100644 xen/arch/x86/cpu/hygon.c

Comments

Pu Wen April 4, 2019, 4:47 p.m. UTC | #1
On 2019/4/4 22:08, Julien Grall wrote:
> Hi,
> 
> I am not sure why I end up to be CCed on the cover letter when I am not CCed on
> the rest of series.

The patch 01/15 of the series is CCed to you. :)
Julien Grall April 4, 2019, 5 p.m. UTC | #2
On 04/04/2019 17:47, Pu Wen wrote:
> On 2019/4/4 22:08, Julien Grall wrote:
>> Hi,
>>
>> I am not sure why I end up to be CCed on the cover letter when I am not CCed on
>> the rest of series.
> 
> The patch 01/15 of the series is CCed to you. :)

I did notice it afterwards. But the code is only x86 specific...

It looks like xen/lib/x86 was not falling under the x86 maintainership. I have 
sent a patch to avoid the "REST" maintainers to be CCed on it.

Cheers,
Andrew Cooper June 6, 2019, 4:31 p.m. UTC | #3
On 04/04/2019 14:44, Pu Wen wrote:
> This patch series have been applied and tested successfully on Hygon
> Dhyana processor, also been tested on AMD EPYC (family 17h) processor.
> It works fine and makes no harm to the existing code.

Hello,

Sorry for the delay.

I've rebased the patches over my CPUID work, and pushed the ones which
still apply cleanly to staging.  However, some don't apply cleanly any
more, so I left those alone.

Please could you check the current staging build (and in particular,
that I didn't accidentally break anything with the rebase), and rebase
the remainder of the series onto staging.

Thanks,

~Andrew
Pu Wen June 7, 2019, 3:54 p.m. UTC | #4
On 2019/6/7 0:31, Andrew Cooper wrote:
> I've rebased the patches over my CPUID work, and pushed the ones which
> still apply cleanly to staging.  However, some don't apply cleanly any

Thanks a lot.

> more, so I left those alone.
> 
> Please could you check the current staging build (and in particular,
> that I didn't accidentally break anything with the rebase), and rebase

Yes, the current staging build is OK and works on Hygon platform.
I'll check the functionalities more carefully.

> the remainder of the series onto staging.

I'll do this later on.

--
Regards,
Pu Wen
Pu Wen June 12, 2019, 3:10 p.m. UTC | #5
On 2019/6/7 0:31, Andrew Cooper wrote:
> I've rebased the patches over my CPUID work, and pushed the ones which
> still apply cleanly to staging.  However, some don't apply cleanly any
> more, so I left those alone.
>
> Please could you check the current staging build (and in particular,
> that I didn't accidentally break anything with the rebase), and rebase
> the remainder of the series onto staging.

I rebased the patches x86/acpi and x86/pv over 0cd07414 "x86/cpu:
Renumber X86_VENDOR_* to form a bitmap", and sent them out with version
v6. I dropped the patch x86/iommu for Hygon because it's no needed any
more since the commit 1b3cc800 "x86/IOMMU: introduce init-ops structure"
removed the vendor check.

I still hold Jan's Acked-by tags however the code is changed. Are the
tags still valid?

Thx.

--
Regards,
Pu Wen
Andrew Cooper June 12, 2019, 3:58 p.m. UTC | #6
On 12/06/2019 16:10, Pu Wen wrote:
> On 2019/6/7 0:31, Andrew Cooper wrote:
>> I've rebased the patches over my CPUID work, and pushed the ones which
>> still apply cleanly to staging.  However, some don't apply cleanly any
>> more, so I left those alone.
>>
>> Please could you check the current staging build (and in particular,
>> that I didn't accidentally break anything with the rebase), and rebase
>> the remainder of the series onto staging.
>
> I rebased the patches x86/acpi and x86/pv over 0cd07414 "x86/cpu:
> Renumber X86_VENDOR_* to form a bitmap", and sent them out with version
> v6. I dropped the patch x86/iommu for Hygon because it's no needed any
> more since the commit 1b3cc800 "x86/IOMMU: introduce init-ops structure"
> removed the vendor check.
>
> I still hold Jan's Acked-by tags however the code is changed. Are the
> tags still valid?

Yes.  The tags were still valid, because you're not fundamentally
changing the patch from how it was before.

I've committed the patches now.

~Andrew