[v2,0/3] drm/meson: implement RDMA for AFBC reset on vsync

Message

Neil Armstrong Oct. 17, 2019, 9:48 a.m. UTC

The VPU embeds a "Register DMA" that can write a sequence of registers
on the VPU AHB bus, either manually or triggered by an internal IRQ
event like VSYNC or a line input counter.

The initial implementation handles a single channel (over 8), triggered
by the VSYNC irq and does not handle the RDMA irq.

The RDMA will be usefull to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.

For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.

When enabled, the RDMA is enabled to rewritte the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.

The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync.

Changes since v1 at [1]:
- Fixed a regression when AFBC was not used, adding a reset() call for the afbc module
- Added a define for the RDMA descriptor size
- Fixed overflow detection

[1] https://patchwork.freedesktop.org/series/68021/#rev1

Neil Armstrong (3):
  drm/meson: add RDMA register bits defines
  drm/meson: add RDMA module driver
  drm/meson: use RDMA to reconfigure AFBC on vsync

 drivers/gpu/drm/meson/Makefile          |   2 +-
 drivers/gpu/drm/meson/meson_crtc.c      |  27 ++---
 drivers/gpu/drm/meson/meson_drv.c       |  14 ++-
 drivers/gpu/drm/meson/meson_drv.h       |   6 ++
 drivers/gpu/drm/meson/meson_osd_afbcd.c | 100 ++++++++++--------
 drivers/gpu/drm/meson/meson_rdma.c      | 132 ++++++++++++++++++++++++
 drivers/gpu/drm/meson/meson_rdma.h      |  21 ++++
 drivers/gpu/drm/meson/meson_registers.h |  48 +++++++++
 8 files changed, 283 insertions(+), 67 deletions(-)
 create mode 100644 drivers/gpu/drm/meson/meson_rdma.c
 create mode 100644 drivers/gpu/drm/meson/meson_rdma.h

Comments

Kevin Hilman Dec. 9, 2019, 10:03 p.m. UTC | #1

Neil Armstrong <[e-mail]> writes:

> The VPU embeds a "Register DMA" that can write a sequence of registers
> on the VPU AHB bus, either manually or triggered by an internal IRQ
> event like VSYNC or a line input counter.
>
> The initial implementation handles a single channel (over 8), triggered
> by the VSYNC irq and does not handle the RDMA irq.
>
> The RDMA will be usefull to reset and program the AFBC decoder unit
> on each vsync without involving the interrupt handler that can
> be masked for a long period of time, producing display glitches.
>
> For this we use the meson_rdma_writel_sync() which adds the register
> write tuple (VPU register offset and register value) to the RDMA buffer
> and write the value to the HW.
>
> When enabled, the RDMA is enabled to rewritte the same sequence at the
> next VSYNC event, until a new buffer is committed to the OSD plane.
>
> The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
> doesn't need a reset/reprogram at each vsync.
>
> Changes since v1 at [1]:
> - Fixed a regression when AFBC was not used, adding a reset() call for the afbc module
> - Added a define for the RDMA descriptor size
> - Fixed overflow detection

Reviewed-by: Kevin Hilman <[e-mail]>