[v6,0/7] Add Bitmain BM1880 clock driver
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Message ID 20191026110253.18426-1-manivannan.sadhasivam@linaro.org
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  • Add Bitmain BM1880 clock driver
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Manivannan Sadhasivam Oct. 26, 2019, 11:02 a.m. UTC
Hello,

This patchset adds common clock driver for Bitmain BM1880 SoC clock
controller. The clock controller consists of gate, divider, mux
and pll clocks with different compositions. Hence, the driver uses
composite clock structure in place where multiple clocking units are
combined together.

This patchset also removes UART fixed clock and sources clocks from clock
controller for Sophon Edge board where the driver has been validated.

Thanks,
Mani

Changes in v6:

* Dropped 'clk: Warn if clk_init_data is not zero initialized' patch
* Added fixes tag to the patch adding 'clk_hw_unregister_composite'
  definition
* Reworked the use of CLK_IS_CTITICAL flag from clk driver
* Removed the use of CLK_DIVIDER_HIWORD_MASK flag from driver
* Some misc cleanups to the driver
* Added Rob's reviewed tag for the binding

Changes in v5:

* Incorporated review comments from Rob on dt binding

Changes in v4:

* Fixed devicetree binding issue
* Added ARCH_BITMAIN as the default for the clk driver

Changes in v3:

* Switched to clk_hw_{register/unregister} APIs
* Returned clk_hw from the in-driver registration helpers

Changes in v2:

* Converted the dt binding to YAML
* Incorporated review comments from Stephen (majority of change is switching
  to new way of specifying clk parents)

Manivannan Sadhasivam (7):
  clk: Zero init clk_init_data in helpers
  clk: Add clk_hw_unregister_composite helper function definition
  dt-bindings: clock: Add devicetree binding for BM1880 SoC
  arm64: dts: bitmain: Add clock controller support for BM1880 SoC
  arm64: dts: bitmain: Source common clock for UART controllers
  clk: Add common clock driver for BM1880 SoC
  MAINTAINERS: Add entry for BM1880 SoC clock driver

 .../bindings/clock/bitmain,bm1880-clk.yaml    |  76 ++
 MAINTAINERS                                   |   2 +
 .../boot/dts/bitmain/bm1880-sophon-edge.dts   |   9 -
 arch/arm64/boot/dts/bitmain/bm1880.dtsi       |  28 +
 drivers/clk/Kconfig                           |   7 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-bm1880.c                      | 970 ++++++++++++++++++
 drivers/clk/clk-composite.c                   |  13 +-
 drivers/clk/clk-divider.c                     |   2 +-
 drivers/clk/clk-fixed-rate.c                  |   2 +-
 drivers/clk/clk-gate.c                        |   2 +-
 drivers/clk/clk-mux.c                         |   2 +-
 include/dt-bindings/clock/bm1880-clock.h      |  82 ++
 13 files changed, 1182 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
 create mode 100644 drivers/clk/clk-bm1880.c
 create mode 100644 include/dt-bindings/clock/bm1880-clock.h

Comments

Stephen Boyd Nov. 13, 2019, 10:21 p.m. UTC | #1
Quoting Manivannan Sadhasivam (2019-10-26 04:02:46)
> Hello,
> 
> This patchset adds common clock driver for Bitmain BM1880 SoC clock
> controller. The clock controller consists of gate, divider, mux
> and pll clocks with different compositions. Hence, the driver uses
> composite clock structure in place where multiple clocking units are
> combined together.
> 
> This patchset also removes UART fixed clock and sources clocks from clock
> controller for Sophon Edge board where the driver has been validated.
> 

Are you waiting for review here? I see some kbuild reports so I assumed
you would fix and resend.
Manivannan Sadhasivam Nov. 14, 2019, 5:34 a.m. UTC | #2
On Wed, Nov 13, 2019 at 02:21:15PM -0800, Stephen Boyd wrote:
> Quoting Manivannan Sadhasivam (2019-10-26 04:02:46)
> > Hello,
> > 
> > This patchset adds common clock driver for Bitmain BM1880 SoC clock
> > controller. The clock controller consists of gate, divider, mux
> > and pll clocks with different compositions. Hence, the driver uses
> > composite clock structure in place where multiple clocking units are
> > combined together.
> > 
> > This patchset also removes UART fixed clock and sources clocks from clock
> > controller for Sophon Edge board where the driver has been validated.
> > 
> 
> Are you waiting for review here? I see some kbuild reports so I assumed
> you would fix and resend.

I'll fix it but I was expecting some review from you so that I can send the
next revision incorporating all comments.

Thanks,
Mani

>
Stephen Boyd Nov. 14, 2019, 5:50 a.m. UTC | #3
Quoting Manivannan Sadhasivam (2019-11-13 21:34:04)
> On Wed, Nov 13, 2019 at 02:21:15PM -0800, Stephen Boyd wrote:
> > Quoting Manivannan Sadhasivam (2019-10-26 04:02:46)
> > > Hello,
> > > 
> > > This patchset adds common clock driver for Bitmain BM1880 SoC clock
> > > controller. The clock controller consists of gate, divider, mux
> > > and pll clocks with different compositions. Hence, the driver uses
> > > composite clock structure in place where multiple clocking units are
> > > combined together.
> > > 
> > > This patchset also removes UART fixed clock and sources clocks from clock
> > > controller for Sophon Edge board where the driver has been validated.
> > > 
> > 
> > Are you waiting for review here? I see some kbuild reports so I assumed
> > you would fix and resend.
> 
> I'll fix it but I was expecting some review from you so that I can send the
> next revision incorporating all comments.
> 

Ok. I'm glad I broke the silence then.

Can you please resend without any dts changes? Those don't go through
clk tree. I think otherwise the patches look OK, although I was hoping
you could register clks by using the new way of specifying parents. Is
that possible?
Manivannan Sadhasivam Nov. 14, 2019, 6:09 a.m. UTC | #4
On Wed, Nov 13, 2019 at 09:50:53PM -0800, Stephen Boyd wrote:
> Quoting Manivannan Sadhasivam (2019-11-13 21:34:04)
> > On Wed, Nov 13, 2019 at 02:21:15PM -0800, Stephen Boyd wrote:
> > > Quoting Manivannan Sadhasivam (2019-10-26 04:02:46)
> > > > Hello,
> > > > 
> > > > This patchset adds common clock driver for Bitmain BM1880 SoC clock
> > > > controller. The clock controller consists of gate, divider, mux
> > > > and pll clocks with different compositions. Hence, the driver uses
> > > > composite clock structure in place where multiple clocking units are
> > > > combined together.
> > > > 
> > > > This patchset also removes UART fixed clock and sources clocks from clock
> > > > controller for Sophon Edge board where the driver has been validated.
> > > > 
> > > 
> > > Are you waiting for review here? I see some kbuild reports so I assumed
> > > you would fix and resend.
> > 
> > I'll fix it but I was expecting some review from you so that I can send the
> > next revision incorporating all comments.
> > 
> 
> Ok. I'm glad I broke the silence then.
> 
> Can you please resend without any dts changes? Those don't go through
> clk tree. 

I'm the platform maintainer, so I'll take the dts changes via ARM SoC tree.

> I think otherwise the patches look OK, although I was hoping
> you could register clks by using the new way of specifying parents. Is
> that possible?
> 

Eventhough I'd like to do, my time is very constrained these days. So please
consider merging it as it is and as I promised, I'll switch to the new way of
specifying parents soon.

Thanks,
Mani