| Message ID | 20191117140731.137378-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | add the DDR clock controller on Meson8 and Meson8b | expand |
On Sun 17 Nov 2019 at 15:07, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS > registers. This series: > - adds support for this DDR clock controller (patches 0 and 1) > - wires up the DDR PLL as input for two audio clocks (patches 2 and 3) > - adds the DDR clock controller to meson8.dtsi and meson8b.dtsi > > Special thanks go out to Alexandre Mergnat for switching the Amlogic > clock drivers over to parent_hws and parent_data. That made this series > a lot easier for me! > > This series depends on v3 my other series from [0]: > "provide the XTAL clock via OF on Meson8/8b/8m2" > > > Changes since v2 at [2]: > - add #include <linux/clk-provider.h> as suggested by Stephen Boyd > - drop unused includes > - use devm_platform_ioremap_resource instead of open-coding it as > suggested by Stephen Boyd > - drop trailing comma after sentinel element as suggested by Stephen > Boyd > - dropped patch #3 "clk: meson: meson8b: use of_clk_hw_register to > register the clocks" because it's now moved to my other series at > [0] > - dropped dts changes so this series exclusively targets clk-meson > > Changes since v1 at [1]: > - fixed the license of the .yaml binding and added Rob's Reviewed-by > - drop unused syscon.h include (spotted by Jerome - thanks) > - drop fast_io from regmap_config and add max_register as suggested > by Jerome > - dropped original patch #4 "clk: meson: meson8b: add the ddr_pll > input for the audio clocks" because I could not test that yet (that > patch was a forward-port from Amlogic's 3.10 BSP kernel) > > > [0] https://patchwork.kernel.org/cover/11248377/ > [1] https://patchwork.kernel.org/cover/11155553/ > [2] https://patchwork.kernel.org/cover/11214227/ > > > Martin Blumenstingl (2): > dt-bindings: clock: add the Amlogic Meson8 DDR clock controller > binding > clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller > > .../clock/amlogic,meson8-ddr-clkc.yaml | 50 ++++++ > drivers/clk/meson/Makefile | 2 +- > drivers/clk/meson/meson8-ddr.c | 149 ++++++++++++++++++ > include/dt-bindings/clock/meson8-ddr-clkc.h | 4 + > 4 files changed, 204 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml > create mode 100644 drivers/clk/meson/meson8-ddr.c > create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h Applied for v5.6 Please note this will get rebased once v5.5-rc1 is out
Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS registers. This series: - adds support for this DDR clock controller (patches 0 and 1) - wires up the DDR PLL as input for two audio clocks (patches 2 and 3) - adds the DDR clock controller to meson8.dtsi and meson8b.dtsi Special thanks go out to Alexandre Mergnat for switching the Amlogic clock drivers over to parent_hws and parent_data. That made this series a lot easier for me! This series depends on v3 my other series from [0]: "provide the XTAL clock via OF on Meson8/8b/8m2" Changes since v2 at [2]: - add #include <linux/clk-provider.h> as suggested by Stephen Boyd - drop unused includes - use devm_platform_ioremap_resource instead of open-coding it as suggested by Stephen Boyd - drop trailing comma after sentinel element as suggested by Stephen Boyd - dropped patch #3 "clk: meson: meson8b: use of_clk_hw_register to register the clocks" because it's now moved to my other series at [0] - dropped dts changes so this series exclusively targets clk-meson Changes since v1 at [1]: - fixed the license of the .yaml binding and added Rob's Reviewed-by - drop unused syscon.h include (spotted by Jerome - thanks) - drop fast_io from regmap_config and add max_register as suggested by Jerome - dropped original patch #4 "clk: meson: meson8b: add the ddr_pll input for the audio clocks" because I could not test that yet (that patch was a forward-port from Amlogic's 3.10 BSP kernel) [0] https://patchwork.kernel.org/cover/11248377/ [1] https://patchwork.kernel.org/cover/11155553/ [2] https://patchwork.kernel.org/cover/11214227/ Martin Blumenstingl (2): dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller .../clock/amlogic,meson8-ddr-clkc.yaml | 50 ++++++ drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8-ddr.c | 149 ++++++++++++++++++ include/dt-bindings/clock/meson8-ddr-clkc.h | 4 + 4 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml create mode 100644 drivers/clk/meson/meson8-ddr.c create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h