[v4,0/7] x86/HVM: implement memory read caching
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Jan Beulich Jan. 31, 2020, 4:37 p.m. UTC
Emulation requiring device model assistance uses a form of instruction
re-execution, assuming that the second (and any further) pass takes
exactly the same path. This is a valid assumption as far as use of CPU
registers goes (as those can't change without any other instruction
executing in between), but is wrong for memory accesses. In particular
it has been observed that Windows might page out buffers underneath
an instruction currently under emulation (hitting between two passes).
If the first pass translated a linear address successfully, any subsequent
pass needs to do so too, yielding the exact same translation.

Introduce a cache to make sure above described assumption holds. This
is a very simplistic implementation for now: Only exact matches are
satisfied (no overlaps or partial reads or anything).

There's also some perhaps seemingly unrelated cleanup here which was
found desirable on the way - the 3 initial patches are truly prereqs
(at least in a contextual way), while the 2 last ones are just for
things noticed along the way.

1: SVM: drop asm/hvm/emulate.h inclusion from vmcb.h
2: x86/HVM: rename a variable in __hvm_copy()
3: x86/HVM: introduce "curr" into hvmemul_rep_{mov,sto}s()
4: x86/HVM: implement memory read caching for insn emulation
5: x86/mm: use cache in guest_walk_tables()
6: x86/mm: drop p2mt parameter from map_domain_gfn()
7: x86/HVM: reduce scope of pfec in hvm_emulate_init_per_insn()

Compared to v3 this is a major re-work to avoid passing around
"cache" arguments, as is my understanding of the main feedback
aspect for v3. I've also dropped (at least for the time being)
add-on patches to seed the cache with PAE PDPTE values.

Jan