[0/1] Enable SSP controller for CS toggle
mbox series

Message ID 20200218134906.25458-1-shobhit.srivastava@intel.com
Headers show
Series
  • Enable SSP controller for CS toggle
Related show

Message

Shobhit Srivastava Feb. 18, 2020, 1:49 p.m. UTC
SPI CS assert may not always be accompanied by data. There are cases
where we want to assert CS, wait and then deassert CS. There is no
clocking or reading required. On Intel CNL LPSS controller, it was
observed that the above flow is broken after an S0ix cycle. There
is no issue after S3 flow.
https://patchwork.kernel.org/patch/11377019/ is an attempt to fix
this and it does fix the issue. However we are unsure if that is
the actual rootcause for the issue. As per the LPSS spec, to
propagate the retained CS to output,  SPI controller needs to be
enabled. The below patch tries to do the same and it fixes the issue.
The reason why there is no issue after S3 flow is because during
resume, BIOS re-initializes and enables SPI before doing kernel hand-off.
To test this issue we are probing the SPI_CS line on CRO. This is
because, even though the mmio writes to CS_CONTROL register sticks,
it doesnt toggle the CS line. Physically probing is the best way
to identify the fix.


Shobhit Srivastava (1):
  spi: pxa2xx: Enable SSP controller for CS toggle

 drivers/spi/spi-pxa2xx.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Mark Brown Feb. 18, 2020, 1:50 p.m. UTC | #1
On Tue, Feb 18, 2020 at 07:19:05PM +0530, Shobhit Srivastava wrote:
> 
> SPI CS assert may not always be accompanied by data. There are cases
> where we want to assert CS, wait and then deassert CS. There is no
> clocking or reading required. On Intel CNL LPSS controller, it was

Please don't send cover letters for single patches, if there is anything
that needs saying put it in the changelog of the patch or after the ---
if it's administrative stuff.  This reduces mail volume and ensures that 
any important information is recorded in the changelog rather than being
lost.