[2/2] drm/i915/huc: Add HuC Load time to dmesg log.
diff mbox

Message ID 1509495081-30501-2-git-send-email-anusha.srivatsa@intel.com
State New
Headers show

Commit Message

Srivatsa, Anusha Nov. 1, 2017, 12:11 a.m. UTC
This patch uses jiffies to calculate the huc
load time.This information can be useful for testing
to know how much time huc takes to load.

v2: Remove debugfs entry. Remove local variable
huc_finish_load. (Daniel, Tvrtko)

v3: Use ktime_get() for more accurate timings.
Ensure the load is successful, before load times
is printed. (Tvrtko, Michal)

v4: Rebase. Do not expose the load time variable in a gobal
struct. Use int for load time (Tvrtko, Joonas)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Oscar Mateo Lozano <oscar.mateo@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_huc.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

Michal Wajdeczko Nov. 1, 2017, 1:32 p.m. UTC | #1
On Wed, 01 Nov 2017 01:11:21 +0100, Anusha Srivatsa  
<anusha.srivatsa@intel.com> wrote:

> This patch uses jiffies to calculate the huc
                   ^^^^^^^                  ^^^
Please update commit message to match final change
and use correct name for HuC (s/huc/HuC)

> load time.This information can be useful for testing
> to know how much time huc takes to load.
>
> v2: Remove debugfs entry. Remove local variable
> huc_finish_load. (Daniel, Tvrtko)
>
> v3: Use ktime_get() for more accurate timings.
> Ensure the load is successful, before load times
> is printed. (Tvrtko, Michal)
>
> v4: Rebase. Do not expose the load time variable in a gobal
> struct. Use int for load time (Tvrtko, Joonas)
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Oscar Mateo Lozano <oscar.mateo@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_huc.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc.c  
> b/drivers/gpu/drm/i915/intel_huc.c
> index 98d1725..3e3ce14 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -127,7 +127,8 @@ static int huc_ucode_xfer(struct intel_uc_fw  
> *huc_fw, struct i915_vma *vma)
>  	struct drm_i915_private *dev_priv = huc_to_i915(huc);
>  	unsigned long offset = 0;
>  	u32 size;
> -	int ret;
> +	int ret, load_time;
> +	ktime_t start_load;
> 	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
> @@ -148,13 +149,19 @@ static int huc_ucode_xfer(struct intel_uc_fw  
> *huc_fw, struct i915_vma *vma)
>  	I915_WRITE(DMA_COPY_SIZE, size);
> 	/* Start the DMA */
> +	start_load = ktime_get();
>  	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> 	/* Wait for DMA to finish */
>  	ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0,  
> 100);
> +	load_time = ktime_ms_delta(ktime_get(), start_load);
> +
>  	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> +	if (!ret)
> +		DRM_DEBUG_DRIVER("HuC is loaded in %d ms\n", load_time);
> +

Maybe we can squash above two messages into:

	DRM_DEBUG_DRIVER("HuC DMA transfer %s in %dms\n",
			 ret ? "timedout" ? "completed",
			 load_time);

>  	/* Disable the bits once DMA is over */
>  	I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 98d1725..3e3ce14 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -127,7 +127,8 @@  static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 	struct drm_i915_private *dev_priv = huc_to_i915(huc);
 	unsigned long offset = 0;
 	u32 size;
-	int ret;
+	int ret, load_time;
+	ktime_t start_load;
 
 	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 
@@ -148,13 +149,19 @@  static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 	I915_WRITE(DMA_COPY_SIZE, size);
 
 	/* Start the DMA */
+	start_load = ktime_get();
 	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 
 	/* Wait for DMA to finish */
 	ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
 
+	load_time = ktime_ms_delta(ktime_get(), start_load);
+
 	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 
+	if (!ret)
+		DRM_DEBUG_DRIVER("HuC is loaded in %d ms\n", load_time);
+
 	/* Disable the bits once DMA is over */
 	I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));