From patchwork Wed Nov 1 00:11:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10035793 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C76B0603B5 for ; Wed, 1 Nov 2017 00:13:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BAD6328B2F for ; Wed, 1 Nov 2017 00:13:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AF97F28B3C; Wed, 1 Nov 2017 00:13:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6975428B2F for ; Wed, 1 Nov 2017 00:13:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F19F66E670; Wed, 1 Nov 2017 00:13:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D277C6E670 for ; Wed, 1 Nov 2017 00:13:46 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Oct 2017 17:13:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,326,1505804400"; d="scan'208";a="144471431" Received: from anusha-dev.jf.intel.com ([10.7.198.179]) by orsmga004.jf.intel.com with ESMTP; 31 Oct 2017 17:13:36 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Oct 2017 17:11:21 -0700 Message-Id: <1509495081-30501-2-git-send-email-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509495081-30501-1-git-send-email-anusha.srivatsa@intel.com> References: <1509495081-30501-1-git-send-email-anusha.srivatsa@intel.com> Cc: Sujaritha Sundaresan , Daniel Vetter Subject: [Intel-gfx] [PATCH 2/2] drm/i915/huc: Add HuC Load time to dmesg log. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch uses jiffies to calculate the huc load time.This information can be useful for testing to know how much time huc takes to load. v2: Remove debugfs entry. Remove local variable huc_finish_load. (Daniel, Tvrtko) v3: Use ktime_get() for more accurate timings. Ensure the load is successful, before load times is printed. (Tvrtko, Michal) v4: Rebase. Do not expose the load time variable in a gobal struct. Use int for load time (Tvrtko, Joonas) Cc: Chris Wilson Cc: Daniel Vetter Cc: Michal Wajdeczko Cc: Oscar Mateo Lozano Cc: Sujaritha Sundaresan Cc: Tvrtko Ursulin Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_huc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 98d1725..3e3ce14 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -127,7 +127,8 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) struct drm_i915_private *dev_priv = huc_to_i915(huc); unsigned long offset = 0; u32 size; - int ret; + int ret, load_time; + ktime_t start_load; GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC); @@ -148,13 +149,19 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma) I915_WRITE(DMA_COPY_SIZE, size); /* Start the DMA */ + start_load = ktime_get(); I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA)); /* Wait for DMA to finish */ ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100); + load_time = ktime_ms_delta(ktime_get(), start_load); + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret); + if (!ret) + DRM_DEBUG_DRIVER("HuC is loaded in %d ms\n", load_time); + /* Disable the bits once DMA is over */ I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));