From patchwork Mon Jul 25 10:20:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 1004132 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6PALcKo001572 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 25 Jul 2011 10:21:59 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QlIHZ-00022c-Q2; Mon, 25 Jul 2011 10:21:06 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QlIHZ-0003YJ-E5; Mon, 25 Jul 2011 10:21:05 +0000 Received: from na3sys009aog105.obsmtp.com ([74.125.149.75]) by canuck.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1QlIHV-0003Y1-Gq for linux-arm-kernel@lists.infradead.org; Mon, 25 Jul 2011 10:21:02 +0000 Received: from mail-gy0-f172.google.com ([209.85.160.172]) (using TLSv1) by na3sys009aob105.postini.com ([74.125.148.12]) with SMTP ID DSNKTi1DilH6FLb0E3F1rTgZDlspvyCAZ56V@postini.com; Mon, 25 Jul 2011 03:21:01 PDT Received: by gyd5 with SMTP id 5so2442871gyd.31 for ; Mon, 25 Jul 2011 03:20:57 -0700 (PDT) Received: by 10.151.29.4 with SMTP id g4mr4055814ybj.164.1311589257750; Mon, 25 Jul 2011 03:20:57 -0700 (PDT) Received: from [172.24.137.243] (dragon.ti.com [192.94.94.33]) by mx.google.com with ESMTPS id z19sm4919703ana.13.2011.07.25.03.20.54 (version=SSLv3 cipher=OTHER); Mon, 25 Jul 2011 03:20:56 -0700 (PDT) Message-ID: <4E2D4383.7050303@ti.com> Date: Mon, 25 Jul 2011 15:50:51 +0530 From: Santosh Shilimkar User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.9.2.15) Gecko/20110303 Thunderbird/3.1.9 MIME-Version: 1.0 To: Thomas Gleixner Subject: Re: IRQCHIP_MASK_ON_SUSPEND and the gic References: In-Reply-To: X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110725_062101_771463_F160528A X-CRM114-Status: GOOD ( 24.37 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.149.75 listed in list.dnswl.org] Cc: Russell King - ARM Linux , linux-arm-kernel@lists.infradead.org, Colin Cross X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 25 Jul 2011 10:22:15 +0000 (UTC) Thomas, On 7/14/2011 7:13 AM, Colin Cross wrote: > Quick background: > The gic is an interrupt controller commonly found in SMP ARM devices. > It has no power management capabilities, and is turned off when the > cpu is powered down in suspend. In order to wake the device out of > suspend, a second interrupt controller is placed in series with the > gic, passing each interrupt through along with a mask. If an unmasked > interrupt is received at the secondary controller, and the cpu is > powered down, a wakeup is triggered. > > In order to keep the cpu from waking on masked interrupts during > cpuidle, the secondary controller masks must be updated at the same > time as the gic masks. This is handled through the gic_arch_extn > irqchip pointer that is filled out by each architecture. > > During suspend, the same registers used by mask/unmask need to be > programmed to have all wakeup interrupts unmasked, and all non-wakeup > interrupts masked. I believe the unmasking is already taken care of: > every interrupt starts as unmasked, and is lazily masked only when an > interrupt arrives while it is disabled. When check_wakeup_irqs is > called in suspend, every interrupt is guaranteed to be either > unmasked, or masked and marked pending. Pending wakeup irqs will > abort suspend, so every wakeup interrupt is guaranteed to be unmasked > after check_wakeup_irqs. > > That leaves masking, which can easily be handled by setting the > IRQCHIP_MASK_ON_SUSPEND flag on the gic irqchip (propagated from the > gic_arch_extn irqchip). > > So, finally, my question: there is nothing for each secondary > interrupt controller driver to do in a set_wake handler, but if its > not implemented, enable_irq_wake will return an error. Is there any > way to avoid implementing an empty set_wake handler? Should the > missing handler not be an error if IRQCHIP_MASK_ON_SUSPEND is set? Any comments on this? I guess some thing like below should remove a need of dummy set_wake() handler for irq_chips with IRQCHIP_MASK_ON_SUSPEND set. diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 0a7840a..cd4bc01 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -467,6 +467,9 @@ static int set_irq_wake_real(unsigned int irq, unsigned int on) struct irq_desc *desc = irq_to_desc(irq); int ret = -ENXIO; + if (irq_desc_get_chip(desc)->flags & IRQCHIP_MASK_ON_SUSPEND) + return 0; + if (desc->irq_data.chip->irq_set_wake) ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on);