| Message ID | 20171122150717.14162-1-maarten.lankhorst@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Nov 22, 2017 at 04:07:17PM +0100, Maarten Lankhorst wrote: > ips_enabled was used as a variable of whether IPS can be enabled or not, > but should be used to test whether IPS is actually enabled. > > Changes since v1: > - Call needs_modeset on new crtc state. (Ville) > - IPS can be enabled with sprite plane enabled too. (Ville) > - Fix CDCLK vs IPS workaround. (Ville) > Changes since v2: > - Only re-enable fastset when inheriting mode. (Ville) > - Put the conditions for enabling and disabling IPS in a helper. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 151 +++++++++++++++++++++------------- > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pipe_crc.c | 2 - > 4 files changed, 98 insertions(+), 58 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > index e8884c2ade98..30affa7903d7 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -1896,7 +1896,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); > > /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > + if (IS_BROADWELL(dev_priv) && hsw_pipe_config_ips_capable(crtc_state)) > min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); > > /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 2007c69468b9..b62cb6e90669 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -489,7 +489,7 @@ static const struct intel_limit intel_limits_bxt = { > }; > > static bool > -needs_modeset(struct drm_crtc_state *state) > +needs_modeset(const struct drm_crtc_state *state) > { > return drm_atomic_crtc_needs_modeset(state); > } > @@ -4870,7 +4870,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > > - if (!crtc->config->ips_enabled) > + if (!crtc_state->ips_enabled) > return; > > /* > @@ -4966,14 +4966,6 @@ intel_post_enable_primary(struct drm_crtc *crtc, > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > int pipe = intel_crtc->pipe; > > - /* > - * FIXME IPS should be fine as long as one plane is > - * enabled, but in practice it seems to have problems > - * when going from primary only to sprite only and vice > - * versa. > - */ > - hsw_enable_ips(new_crtc_state); > - > /* > * Gen2 reports pipe underruns whenever all planes are disabled. > * So don't enable underrun reporting before at least some planes > @@ -4989,10 +4981,9 @@ intel_post_enable_primary(struct drm_crtc *crtc, > intel_check_pch_fifo_underruns(dev_priv); > } > > -/* FIXME move all this to pre_plane_update() with proper state tracking */ > +/* FIXME get rid of this and use pre_plane_update */ > static void > -intel_pre_disable_primary(struct drm_crtc *crtc, > - const struct intel_crtc_state *old_crtc_state) > +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = to_i915(dev); > @@ -5001,32 +4992,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc, > > /* > * Gen2 reports pipe underruns whenever all planes are disabled. > - * So diasble underrun reporting before all the planes get disabled. > - * FIXME: Need to fix the logic to work when we turn off all planes > - * but leave the pipe running. > + * So disable underrun reporting before all the planes get disabled. > */ > if (IS_GEN2(dev_priv)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); > > - /* > - * FIXME IPS should be fine as long as one plane is > - * enabled, but in practice it seems to have problems > - * when going from primary only to sprite only and vice > - * versa. > - */ > - hsw_disable_ips(old_crtc_state); > -} > - > -/* FIXME get rid of this and use pre_plane_update */ > -static void > -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) > -{ > - struct drm_device *dev = crtc->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - int pipe = intel_crtc->pipe; > - > - intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state)); > + hsw_disable_ips(to_intel_crtc_state(crtc->state)); > > /* > * Vblank time updates from the shadow to live plane control register > @@ -5042,6 +5013,38 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) > intel_wait_for_vblank(dev_priv, pipe); > } > > +static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, > + const struct intel_crtc_state *new_crtc_state) > +{ > + if (!old_crtc_state->ips_enabled) > + return false; > + > + if (needs_modeset(&new_crtc_state->base)) > + return true; > + > + return !new_crtc_state->ips_enabled; > +} > + > +static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, > + const struct intel_crtc_state *new_crtc_state) > +{ > + if (!new_crtc_state->ips_enabled) > + return false; > + > + if (needs_modeset(&new_crtc_state->base)) > + return true; > + > + /* > + * We can't read out IPS on broadwell, assume the worst and > + * forcibly enable IPS on the first fastset. > + */ > + if (new_crtc_state->update_pipe && > + old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED) > + return true; > + > + return !old_crtc_state->ips_enabled; > +} > + > static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); > @@ -5058,6 +5061,9 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) > if (pipe_config->update_wm_post && pipe_config->base.active) > intel_update_watermarks(crtc); > > + if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) > + hsw_enable_ips(pipe_config); > + > if (old_pri_state) { > struct intel_plane_state *primary_state = > intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), > @@ -5088,6 +5094,9 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, > struct intel_atomic_state *old_intel_state = > to_intel_atomic_state(old_state); > > + if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) > + hsw_disable_ips(old_crtc_state); > + > if (old_pri_state) { > struct intel_plane_state *primary_state = > intel_atomic_get_new_plane_state(old_intel_state, > @@ -5096,10 +5105,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, > to_intel_plane_state(old_pri_state); > > intel_fbc_pre_update(crtc, pipe_config, primary_state); > - > - if (old_primary_state->base.visible && > + /* > + * Gen2 reports pipe underruns whenever all planes are disabled. > + * So disable underrun reporting before all the planes get disabled. > + */ > + if (IS_GEN2(dev_priv) && old_primary_state->base.visible && > (modeset || !primary_state->base.visible)) > - intel_pre_disable_primary(&crtc->base, old_crtc_state); > + intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); > } > > /* > @@ -6228,15 +6240,42 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, > return ret; > } > > -static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, > - struct intel_crtc_state *pipe_config) > +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config) > { > - if (pipe_config->ips_force_disable) > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); > + > + /* IPS only exists on ULT machines and is tied to pipe A. */ > + if (!hsw_crtc_supports_ips(crtc)) > + return false; > + > + if (!i915_modparams.enable_ips) > return false; > > if (pipe_config->pipe_bpp > 24) > return false; > > + return true; The max_cdclk check should be here. Otherwise this looks quite nice. Maybe also re-add the ips_enabled vs. hw state assert on HSW? I guess intel_verify_planes() migth be a nice place for it, in case we ever decide to start doing these checks for pure plane updates as well... > +} > + > +static bool hsw_compute_ips_config(struct intel_crtc_state *pipe_config) > +{ > + struct drm_i915_private *dev_priv = to_i915(pipe_config->base.crtc->dev); > + > + if (!hsw_pipe_config_ips_capable(pipe_config)) > + return false; > + > + if (pipe_config->ips_force_disable) > + return false; > + > + /* > + * FIXME IPS should be fine as long as one plane is > + * enabled, but in practice it seems to have problems > + * when going from primary only to sprite only and vice > + * versa. > + */ > + if (!(pipe_config->active_planes & BIT(PLANE_PRIMARY))) > + return false; > + > /* HSW can handle pixel rate up to cdclk? */ > if (IS_HASWELL(dev_priv)) > return true; > @@ -6252,17 +6291,6 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, > dev_priv->max_cdclk_freq * 95 / 100; > } > > -static void hsw_compute_ips_config(struct intel_crtc *crtc, > - struct intel_crtc_state *pipe_config) > -{ > - struct drm_device *dev = crtc->base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > - > - pipe_config->ips_enabled = i915_modparams.enable_ips && > - hsw_crtc_supports_ips(crtc) && > - pipe_config_supports_ips(dev_priv, pipe_config); > -} > - > static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) > { > const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > @@ -6378,9 +6406,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > > intel_crtc_compute_pixel_rate(pipe_config); > > - if (HAS_IPS(dev_priv)) > - hsw_compute_ips_config(crtc, pipe_config); > - > if (pipe_config->has_pch_encoder) > return ironlake_fdi_compute_config(crtc, pipe_config); > > @@ -9275,6 +9300,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > ironlake_get_pfit_config(crtc, pipe_config); > } > > + if (hsw_crtc_supports_ips(crtc)) { > + if (IS_HASWELL(dev_priv)) > + pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; > + else { > + /* > + * We cannot readout IPS state on broadwell, set to > + * true so we can set it to a defined state on first > + * commit. > + */ > + pipe_config->ips_enabled = true; > + } > + } > + > if (pipe_config->cpu_transcoder != TRANSCODER_EDP && > !transcoder_is_dsi(pipe_config->cpu_transcoder)) { > pipe_config->pixel_multiplier = > @@ -10489,6 +10527,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, > pipe_config); > } > > + if (HAS_IPS(dev_priv)) > + pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config); > + > return ret; > } > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 69aab324aaa1..40417b20844e 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1485,6 +1485,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, > int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); > > bool intel_crtc_active(struct intel_crtc *crtc); > +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config); > void hsw_enable_ips(const struct intel_crtc_state *crtc_state); > void hsw_disable_ips(const struct intel_crtc_state *crtc_state); > enum intel_display_power_domain intel_port_to_power_domain(enum port port); > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > index 61641d479b93..1f5cd572a7ff 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -541,8 +541,6 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv, > * completely disable it. > */ > pipe_config->ips_force_disable = enable; > - if (pipe_config->ips_enabled == enable) > - pipe_config->base.connectors_changed = true; > } > > if (IS_HASWELL(dev_priv)) { > -- > 2.15.0
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index e8884c2ade98..30affa7903d7 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1896,7 +1896,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) + if (IS_BROADWELL(dev_priv) && hsw_pipe_config_ips_capable(crtc_state)) min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2007c69468b9..b62cb6e90669 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -489,7 +489,7 @@ static const struct intel_limit intel_limits_bxt = { }; static bool -needs_modeset(struct drm_crtc_state *state) +needs_modeset(const struct drm_crtc_state *state) { return drm_atomic_crtc_needs_modeset(state); } @@ -4870,7 +4870,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - if (!crtc->config->ips_enabled) + if (!crtc_state->ips_enabled) return; /* @@ -4966,14 +4966,6 @@ intel_post_enable_primary(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_crtc->pipe; - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_enable_ips(new_crtc_state); - /* * Gen2 reports pipe underruns whenever all planes are disabled. * So don't enable underrun reporting before at least some planes @@ -4989,10 +4981,9 @@ intel_post_enable_primary(struct drm_crtc *crtc, intel_check_pch_fifo_underruns(dev_priv); } -/* FIXME move all this to pre_plane_update() with proper state tracking */ +/* FIXME get rid of this and use pre_plane_update */ static void -intel_pre_disable_primary(struct drm_crtc *crtc, - const struct intel_crtc_state *old_crtc_state) +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -5001,32 +4992,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc, /* * Gen2 reports pipe underruns whenever all planes are disabled. - * So diasble underrun reporting before all the planes get disabled. - * FIXME: Need to fix the logic to work when we turn off all planes - * but leave the pipe running. + * So disable underrun reporting before all the planes get disabled. */ if (IS_GEN2(dev_priv)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_disable_ips(old_crtc_state); -} - -/* FIXME get rid of this and use pre_plane_update */ -static void -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - int pipe = intel_crtc->pipe; - - intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state)); + hsw_disable_ips(to_intel_crtc_state(crtc->state)); /* * Vblank time updates from the shadow to live plane control register @@ -5042,6 +5013,38 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) intel_wait_for_vblank(dev_priv, pipe); } +static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!old_crtc_state->ips_enabled) + return false; + + if (needs_modeset(&new_crtc_state->base)) + return true; + + return !new_crtc_state->ips_enabled; +} + +static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->ips_enabled) + return false; + + if (needs_modeset(&new_crtc_state->base)) + return true; + + /* + * We can't read out IPS on broadwell, assume the worst and + * forcibly enable IPS on the first fastset. + */ + if (new_crtc_state->update_pipe && + old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED) + return true; + + return !old_crtc_state->ips_enabled; +} + static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); @@ -5058,6 +5061,9 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) if (pipe_config->update_wm_post && pipe_config->base.active) intel_update_watermarks(crtc); + if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) + hsw_enable_ips(pipe_config); + if (old_pri_state) { struct intel_plane_state *primary_state = intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), @@ -5088,6 +5094,9 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, struct intel_atomic_state *old_intel_state = to_intel_atomic_state(old_state); + if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) + hsw_disable_ips(old_crtc_state); + if (old_pri_state) { struct intel_plane_state *primary_state = intel_atomic_get_new_plane_state(old_intel_state, @@ -5096,10 +5105,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, to_intel_plane_state(old_pri_state); intel_fbc_pre_update(crtc, pipe_config, primary_state); - - if (old_primary_state->base.visible && + /* + * Gen2 reports pipe underruns whenever all planes are disabled. + * So disable underrun reporting before all the planes get disabled. + */ + if (IS_GEN2(dev_priv) && old_primary_state->base.visible && (modeset || !primary_state->base.visible)) - intel_pre_disable_primary(&crtc->base, old_crtc_state); + intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); } /* @@ -6228,15 +6240,42 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, return ret; } -static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, - struct intel_crtc_state *pipe_config) +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config) { - if (pipe_config->ips_force_disable) + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); + + /* IPS only exists on ULT machines and is tied to pipe A. */ + if (!hsw_crtc_supports_ips(crtc)) + return false; + + if (!i915_modparams.enable_ips) return false; if (pipe_config->pipe_bpp > 24) return false; + return true; +} + +static bool hsw_compute_ips_config(struct intel_crtc_state *pipe_config) +{ + struct drm_i915_private *dev_priv = to_i915(pipe_config->base.crtc->dev); + + if (!hsw_pipe_config_ips_capable(pipe_config)) + return false; + + if (pipe_config->ips_force_disable) + return false; + + /* + * FIXME IPS should be fine as long as one plane is + * enabled, but in practice it seems to have problems + * when going from primary only to sprite only and vice + * versa. + */ + if (!(pipe_config->active_planes & BIT(PLANE_PRIMARY))) + return false; + /* HSW can handle pixel rate up to cdclk? */ if (IS_HASWELL(dev_priv)) return true; @@ -6252,17 +6291,6 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, dev_priv->max_cdclk_freq * 95 / 100; } -static void hsw_compute_ips_config(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - - pipe_config->ips_enabled = i915_modparams.enable_ips && - hsw_crtc_supports_ips(crtc) && - pipe_config_supports_ips(dev_priv, pipe_config); -} - static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) { const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -6378,9 +6406,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, intel_crtc_compute_pixel_rate(pipe_config); - if (HAS_IPS(dev_priv)) - hsw_compute_ips_config(crtc, pipe_config); - if (pipe_config->has_pch_encoder) return ironlake_fdi_compute_config(crtc, pipe_config); @@ -9275,6 +9300,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, ironlake_get_pfit_config(crtc, pipe_config); } + if (hsw_crtc_supports_ips(crtc)) { + if (IS_HASWELL(dev_priv)) + pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; + else { + /* + * We cannot readout IPS state on broadwell, set to + * true so we can set it to a defined state on first + * commit. + */ + pipe_config->ips_enabled = true; + } + } + if (pipe_config->cpu_transcoder != TRANSCODER_EDP && !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = @@ -10489,6 +10527,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, pipe_config); } + if (HAS_IPS(dev_priv)) + pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config); + return ret; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 69aab324aaa1..40417b20844e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1485,6 +1485,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); bool intel_crtc_active(struct intel_crtc *crtc); +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config); void hsw_enable_ips(const struct intel_crtc_state *crtc_state); void hsw_disable_ips(const struct intel_crtc_state *crtc_state); enum intel_display_power_domain intel_port_to_power_domain(enum port port); diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index 61641d479b93..1f5cd572a7ff 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -541,8 +541,6 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv, * completely disable it. */ pipe_config->ips_force_disable = enable; - if (pipe_config->ips_enabled == enable) - pipe_config->base.connectors_changed = true; } if (IS_HASWELL(dev_priv)) {
ips_enabled was used as a variable of whether IPS can be enabled or not, but should be used to test whether IPS is actually enabled. Changes since v1: - Call needs_modeset on new crtc state. (Ville) - IPS can be enabled with sprite plane enabled too. (Ville) - Fix CDCLK vs IPS workaround. (Ville) Changes since v2: - Only re-enable fastset when inheriting mode. (Ville) - Put the conditions for enabling and disabling IPS in a helper. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> --- drivers/gpu/drm/i915/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 151 +++++++++++++++++++++------------- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pipe_crc.c | 2 - 4 files changed, 98 insertions(+), 58 deletions(-)