Message ID | 20171122183901.47720-1-maarten.lankhorst@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Wed, Nov 22, 2017 at 07:39:01PM +0100, Maarten Lankhorst wrote: > ips_enabled was used as a variable of whether IPS can be enabled or not, > but should be used to test whether IPS is actually enabled. > > Changes since v1: > - Call needs_modeset on new crtc state. (Ville) > - IPS can be enabled with sprite plane enabled too. (Ville) > - Fix CDCLK vs IPS workaround. (Ville) > Changes since v2: > - Only re-enable fastset when inheriting mode. (Ville) > - Put the conditions for enabling and disabling IPS in a helper. > Changes since v3: > - Keep the max_cdclk workaround working. (Ville) > - Also check logical cdclk out of paranoia. > - Remove planes check from IPS disable function for initial disable. > - Remove assert_plane_enabled/disabled checks and use > crtc_state->active_planes for hsw_enable_ips only, always allow > calling hsw_disable_ips to disable it initially in hw. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 168 ++++++++++++++++++++++------------ > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pipe_crc.c | 2 - > 4 files changed, 109 insertions(+), 64 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > index e8884c2ade98..30affa7903d7 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -1896,7 +1896,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); > > /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > + if (IS_BROADWELL(dev_priv) && hsw_pipe_config_ips_capable(crtc_state)) > min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); > > /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 60d0a2d8534c..95df5c2128b4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -489,7 +489,7 @@ static const struct intel_limit intel_limits_bxt = { > }; > > static bool > -needs_modeset(struct drm_crtc_state *state) > +needs_modeset(const struct drm_crtc_state *state) > { > return drm_atomic_crtc_needs_modeset(state); > } > @@ -4833,7 +4833,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > > - if (!crtc->config->ips_enabled) > + if (!crtc_state->ips_enabled) > return; > > /* > @@ -4841,8 +4841,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) > * This function is called from post_plane_update, which is run after > * a vblank wait. > */ > - > - assert_plane_enabled(to_intel_plane(crtc->base.primary)); > + WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); > > if (IS_BROADWELL(dev_priv)) { > mutex_lock(&dev_priv->pcu_lock); > @@ -4877,8 +4876,6 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) > if (!crtc_state->ips_enabled) > return; > > - assert_plane_enabled(to_intel_plane(crtc->base.primary)); > - > if (IS_BROADWELL(dev_priv)) { > mutex_lock(&dev_priv->pcu_lock); > WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); > @@ -4931,14 +4928,6 @@ intel_post_enable_primary(struct drm_crtc *crtc, > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > int pipe = intel_crtc->pipe; > > - /* > - * FIXME IPS should be fine as long as one plane is > - * enabled, but in practice it seems to have problems > - * when going from primary only to sprite only and vice > - * versa. > - */ > - hsw_enable_ips(new_crtc_state); > - > /* > * Gen2 reports pipe underruns whenever all planes are disabled. > * So don't enable underrun reporting before at least some planes > @@ -4954,10 +4943,9 @@ intel_post_enable_primary(struct drm_crtc *crtc, > intel_check_pch_fifo_underruns(dev_priv); > } > > -/* FIXME move all this to pre_plane_update() with proper state tracking */ > +/* FIXME get rid of this and use pre_plane_update */ > static void > -intel_pre_disable_primary(struct drm_crtc *crtc, > - const struct intel_crtc_state *old_crtc_state) > +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = to_i915(dev); > @@ -4966,32 +4954,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc, > > /* > * Gen2 reports pipe underruns whenever all planes are disabled. > - * So diasble underrun reporting before all the planes get disabled. > - * FIXME: Need to fix the logic to work when we turn off all planes > - * but leave the pipe running. > + * So disable underrun reporting before all the planes get disabled. > */ > if (IS_GEN2(dev_priv)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); > > - /* > - * FIXME IPS should be fine as long as one plane is > - * enabled, but in practice it seems to have problems > - * when going from primary only to sprite only and vice > - * versa. > - */ > - hsw_disable_ips(old_crtc_state); > -} > - > -/* FIXME get rid of this and use pre_plane_update */ > -static void > -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) > -{ > - struct drm_device *dev = crtc->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > - int pipe = intel_crtc->pipe; > - > - intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state)); > + hsw_disable_ips(to_intel_crtc_state(crtc->state)); > > /* > * Vblank time updates from the shadow to live plane control register > @@ -5007,6 +4975,38 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) > intel_wait_for_vblank(dev_priv, pipe); > } > > +static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, > + const struct intel_crtc_state *new_crtc_state) > +{ > + if (!old_crtc_state->ips_enabled) > + return false; > + > + if (needs_modeset(&new_crtc_state->base)) > + return true; > + > + return !new_crtc_state->ips_enabled; > +} > + > +static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, > + const struct intel_crtc_state *new_crtc_state) > +{ > + if (!new_crtc_state->ips_enabled) > + return false; > + > + if (needs_modeset(&new_crtc_state->base)) > + return true; > + > + /* > + * We can't read out IPS on broadwell, assume the worst and > + * forcibly enable IPS on the first fastset. > + */ > + if (new_crtc_state->update_pipe && Do we even need the update_pipe check now? Ie. why would we skip this if the initial update happens to update just the planes? > + old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED) > + return true; > + > + return !old_crtc_state->ips_enabled; > +} > + > static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); > @@ -5023,6 +5023,9 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) > if (pipe_config->update_wm_post && pipe_config->base.active) > intel_update_watermarks(crtc); > > + if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) > + hsw_enable_ips(pipe_config); > + > if (old_pri_state) { > struct intel_plane_state *primary_state = > intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), > @@ -5053,6 +5056,9 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, > struct intel_atomic_state *old_intel_state = > to_intel_atomic_state(old_state); > > + if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) > + hsw_disable_ips(old_crtc_state); > + > if (old_pri_state) { > struct intel_plane_state *primary_state = > intel_atomic_get_new_plane_state(old_intel_state, > @@ -5061,10 +5067,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, > to_intel_plane_state(old_pri_state); > > intel_fbc_pre_update(crtc, pipe_config, primary_state); > - > - if (old_primary_state->base.visible && > + /* > + * Gen2 reports pipe underruns whenever all planes are disabled. > + * So disable underrun reporting before all the planes get disabled. > + */ > + if (IS_GEN2(dev_priv) && old_primary_state->base.visible && > (modeset || !primary_state->base.visible)) > - intel_pre_disable_primary(&crtc->base, old_crtc_state); > + intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); > } > > /* > @@ -6195,18 +6204,20 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, > return ret; > } > > -static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, > - struct intel_crtc_state *pipe_config) > +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config) Since you're touching pretty much everything, how about s/pipe_config/crtc_state/ while at it? > { > - if (pipe_config->ips_force_disable) > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + > + /* IPS only exists on ULT machines and is tied to pipe A. */ > + if (!hsw_crtc_supports_ips(crtc)) > return false; > > - if (pipe_config->pipe_bpp > 24) > + if (!i915_modparams.enable_ips) > return false; > > - /* HSW can handle pixel rate up to cdclk? */ > - if (IS_HASWELL(dev_priv)) > - return true; > + if (pipe_config->pipe_bpp > 24) > + return false; > > /* > * We compare against max which means we must take > @@ -6215,19 +6226,41 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, > * > * Should measure whether using a lower cdclk w/o IPS > */ > - return pipe_config->pixel_rate <= > - dev_priv->max_cdclk_freq * 95 / 100; > + if (IS_BROADWELL(dev_priv) && pipe_config->pixel_rate > > + dev_priv->max_cdclk_freq * 95 / 100) Splitting the line like that makes it pretty hard to read. if (IS_BROADWELL(...) && pipe_config->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) would look much better IMO. > + return false; > + > + return true; > } > > -static void hsw_compute_ips_config(struct intel_crtc *crtc, > - struct intel_crtc_state *pipe_config) > +static bool hsw_compute_ips_config(struct intel_crtc_state *pipe_config) s/pipe_config/crtc_state/ again > { > - struct drm_device *dev = crtc->base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > + struct drm_i915_private *dev_priv = > + to_i915(pipe_config->base.crtc->dev); > + struct intel_atomic_state *intel_state = > + to_intel_atomic_state(pipe_config->base.state); > + > + if (!hsw_pipe_config_ips_capable(pipe_config)) > + return false; > + > + if (pipe_config->ips_force_disable) > + return false; > + > + /* > + * FIXME IPS should be fine as long as one plane is > + * enabled, but in practice it seems to have problems > + * when going from primary only to sprite only and vice > + * versa. > + */ > + if (!(pipe_config->active_planes & BIT(PLANE_PRIMARY))) > + return false; > > - pipe_config->ips_enabled = i915_modparams.enable_ips && > - hsw_crtc_supports_ips(crtc) && > - pipe_config_supports_ips(dev_priv, pipe_config); > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > + if (IS_BROADWELL(dev_priv) && pipe_config->pixel_rate > > + intel_state->cdclk.logical.cdclk * 95 / 100) > + return false; Another hard to read split. Apart from those nits, this lgtm so Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > + > + return true; > } > > static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) > @@ -6345,9 +6378,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > > intel_crtc_compute_pixel_rate(pipe_config); > > - if (HAS_IPS(dev_priv)) > - hsw_compute_ips_config(crtc, pipe_config); > - > if (pipe_config->has_pch_encoder) > return ironlake_fdi_compute_config(crtc, pipe_config); > > @@ -9183,6 +9213,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > ironlake_get_pfit_config(crtc, pipe_config); > } > > + if (hsw_crtc_supports_ips(crtc)) { > + if (IS_HASWELL(dev_priv)) > + pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; > + else { > + /* > + * We cannot readout IPS state on broadwell, set to > + * true so we can set it to a defined state on first > + * commit. > + */ > + pipe_config->ips_enabled = true; > + } > + } > + > if (pipe_config->cpu_transcoder != TRANSCODER_EDP && > !transcoder_is_dsi(pipe_config->cpu_transcoder)) { > pipe_config->pixel_multiplier = > @@ -10436,6 +10479,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, > pipe_config); > } > > + if (HAS_IPS(dev_priv)) > + pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config); > + > return ret; > } > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 635a96fcd788..4f4cf5128e0c 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1485,6 +1485,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, > int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); > > bool intel_crtc_active(struct intel_crtc *crtc); > +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config); > void hsw_enable_ips(const struct intel_crtc_state *crtc_state); > void hsw_disable_ips(const struct intel_crtc_state *crtc_state); > enum intel_display_power_domain intel_port_to_power_domain(enum port port); > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > index 61641d479b93..1f5cd572a7ff 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -541,8 +541,6 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv, > * completely disable it. > */ > pipe_config->ips_force_disable = enable; > - if (pipe_config->ips_enabled == enable) > - pipe_config->base.connectors_changed = true; > } > > if (IS_HASWELL(dev_priv)) { > -- > 2.15.0
Op 23-11-17 om 15:36 schreef Ville Syrjälä: > On Wed, Nov 22, 2017 at 07:39:01PM +0100, Maarten Lankhorst wrote: >> ips_enabled was used as a variable of whether IPS can be enabled or not, >> but should be used to test whether IPS is actually enabled. >> >> Changes since v1: >> - Call needs_modeset on new crtc state. (Ville) >> - IPS can be enabled with sprite plane enabled too. (Ville) >> - Fix CDCLK vs IPS workaround. (Ville) >> Changes since v2: >> - Only re-enable fastset when inheriting mode. (Ville) >> - Put the conditions for enabling and disabling IPS in a helper. >> Changes since v3: >> - Keep the max_cdclk workaround working. (Ville) >> - Also check logical cdclk out of paranoia. >> - Remove planes check from IPS disable function for initial disable. >> - Remove assert_plane_enabled/disabled checks and use >> crtc_state->active_planes for hsw_enable_ips only, always allow >> calling hsw_disable_ips to disable it initially in hw. >> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> >> --- >> drivers/gpu/drm/i915/intel_cdclk.c | 2 +- >> drivers/gpu/drm/i915/intel_display.c | 168 ++++++++++++++++++++++------------ >> drivers/gpu/drm/i915/intel_drv.h | 1 + >> drivers/gpu/drm/i915/intel_pipe_crc.c | 2 - >> 4 files changed, 109 insertions(+), 64 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c >> index e8884c2ade98..30affa7903d7 100644 >> --- a/drivers/gpu/drm/i915/intel_cdclk.c >> +++ b/drivers/gpu/drm/i915/intel_cdclk.c >> @@ -1896,7 +1896,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) >> min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); >> >> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ >> - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) >> + if (IS_BROADWELL(dev_priv) && hsw_pipe_config_ips_capable(crtc_state)) >> min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); >> >> /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index 60d0a2d8534c..95df5c2128b4 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -489,7 +489,7 @@ static const struct intel_limit intel_limits_bxt = { >> }; >> >> static bool >> -needs_modeset(struct drm_crtc_state *state) >> +needs_modeset(const struct drm_crtc_state *state) >> { >> return drm_atomic_crtc_needs_modeset(state); >> } >> @@ -4833,7 +4833,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) >> struct drm_device *dev = crtc->base.dev; >> struct drm_i915_private *dev_priv = to_i915(dev); >> >> - if (!crtc->config->ips_enabled) >> + if (!crtc_state->ips_enabled) >> return; >> >> /* >> @@ -4841,8 +4841,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) >> * This function is called from post_plane_update, which is run after >> * a vblank wait. >> */ >> - >> - assert_plane_enabled(to_intel_plane(crtc->base.primary)); >> + WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); >> >> if (IS_BROADWELL(dev_priv)) { >> mutex_lock(&dev_priv->pcu_lock); >> @@ -4877,8 +4876,6 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) >> if (!crtc_state->ips_enabled) >> return; >> >> - assert_plane_enabled(to_intel_plane(crtc->base.primary)); >> - >> if (IS_BROADWELL(dev_priv)) { >> mutex_lock(&dev_priv->pcu_lock); >> WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); >> @@ -4931,14 +4928,6 @@ intel_post_enable_primary(struct drm_crtc *crtc, >> struct intel_crtc *intel_crtc = to_intel_crtc(crtc); >> int pipe = intel_crtc->pipe; >> >> - /* >> - * FIXME IPS should be fine as long as one plane is >> - * enabled, but in practice it seems to have problems >> - * when going from primary only to sprite only and vice >> - * versa. >> - */ >> - hsw_enable_ips(new_crtc_state); >> - >> /* >> * Gen2 reports pipe underruns whenever all planes are disabled. >> * So don't enable underrun reporting before at least some planes >> @@ -4954,10 +4943,9 @@ intel_post_enable_primary(struct drm_crtc *crtc, >> intel_check_pch_fifo_underruns(dev_priv); >> } >> >> -/* FIXME move all this to pre_plane_update() with proper state tracking */ >> +/* FIXME get rid of this and use pre_plane_update */ >> static void >> -intel_pre_disable_primary(struct drm_crtc *crtc, >> - const struct intel_crtc_state *old_crtc_state) >> +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) >> { >> struct drm_device *dev = crtc->dev; >> struct drm_i915_private *dev_priv = to_i915(dev); >> @@ -4966,32 +4954,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc, >> >> /* >> * Gen2 reports pipe underruns whenever all planes are disabled. >> - * So diasble underrun reporting before all the planes get disabled. >> - * FIXME: Need to fix the logic to work when we turn off all planes >> - * but leave the pipe running. >> + * So disable underrun reporting before all the planes get disabled. >> */ >> if (IS_GEN2(dev_priv)) >> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); >> >> - /* >> - * FIXME IPS should be fine as long as one plane is >> - * enabled, but in practice it seems to have problems >> - * when going from primary only to sprite only and vice >> - * versa. >> - */ >> - hsw_disable_ips(old_crtc_state); >> -} >> - >> -/* FIXME get rid of this and use pre_plane_update */ >> -static void >> -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) >> -{ >> - struct drm_device *dev = crtc->dev; >> - struct drm_i915_private *dev_priv = to_i915(dev); >> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); >> - int pipe = intel_crtc->pipe; >> - >> - intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state)); >> + hsw_disable_ips(to_intel_crtc_state(crtc->state)); >> >> /* >> * Vblank time updates from the shadow to live plane control register >> @@ -5007,6 +4975,38 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) >> intel_wait_for_vblank(dev_priv, pipe); >> } >> >> +static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, >> + const struct intel_crtc_state *new_crtc_state) >> +{ >> + if (!old_crtc_state->ips_enabled) >> + return false; >> + >> + if (needs_modeset(&new_crtc_state->base)) >> + return true; >> + >> + return !new_crtc_state->ips_enabled; >> +} >> + >> +static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, >> + const struct intel_crtc_state *new_crtc_state) >> +{ >> + if (!new_crtc_state->ips_enabled) >> + return false; >> + >> + if (needs_modeset(&new_crtc_state->base)) >> + return true; >> + >> + /* >> + * We can't read out IPS on broadwell, assume the worst and >> + * forcibly enable IPS on the first fastset. >> + */ >> + if (new_crtc_state->update_pipe && > Do we even need the update_pipe check now? Ie. why would we skip this if the > initial update happens to update just the planes? The first update may update planes, but that keeps the I915_MODE_FLAG_INHERITED flag, we can either choose to keep updating IPS until first update_pipe is called, or only call ips_enabled after first update_pipe. >> + old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED) >> + return true; >> + >> + return !old_crtc_state->ips_enabled; >> +} >> + >> static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) >> { >> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); >> @@ -5023,6 +5023,9 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) >> if (pipe_config->update_wm_post && pipe_config->base.active) >> intel_update_watermarks(crtc); >> >> + if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) >> + hsw_enable_ips(pipe_config); >> + >> if (old_pri_state) { >> struct intel_plane_state *primary_state = >> intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), >> @@ -5053,6 +5056,9 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, >> struct intel_atomic_state *old_intel_state = >> to_intel_atomic_state(old_state); >> >> + if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) >> + hsw_disable_ips(old_crtc_state); >> + >> if (old_pri_state) { >> struct intel_plane_state *primary_state = >> intel_atomic_get_new_plane_state(old_intel_state, >> @@ -5061,10 +5067,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, >> to_intel_plane_state(old_pri_state); >> >> intel_fbc_pre_update(crtc, pipe_config, primary_state); >> - >> - if (old_primary_state->base.visible && >> + /* >> + * Gen2 reports pipe underruns whenever all planes are disabled. >> + * So disable underrun reporting before all the planes get disabled. >> + */ >> + if (IS_GEN2(dev_priv) && old_primary_state->base.visible && >> (modeset || !primary_state->base.visible)) >> - intel_pre_disable_primary(&crtc->base, old_crtc_state); >> + intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); >> } >> >> /* >> @@ -6195,18 +6204,20 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, >> return ret; >> } >> >> -static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, >> - struct intel_crtc_state *pipe_config) >> +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config) > Since you're touching pretty much everything, how about > s/pipe_config/crtc_state/ while at it? > >> { >> - if (pipe_config->ips_force_disable) >> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); >> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> + >> + /* IPS only exists on ULT machines and is tied to pipe A. */ >> + if (!hsw_crtc_supports_ips(crtc)) >> return false; >> >> - if (pipe_config->pipe_bpp > 24) >> + if (!i915_modparams.enable_ips) >> return false; >> >> - /* HSW can handle pixel rate up to cdclk? */ >> - if (IS_HASWELL(dev_priv)) >> - return true; >> + if (pipe_config->pipe_bpp > 24) >> + return false; >> >> /* >> * We compare against max which means we must take >> @@ -6215,19 +6226,41 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, >> * >> * Should measure whether using a lower cdclk w/o IPS >> */ >> - return pipe_config->pixel_rate <= >> - dev_priv->max_cdclk_freq * 95 / 100; >> + if (IS_BROADWELL(dev_priv) && pipe_config->pixel_rate > >> + dev_priv->max_cdclk_freq * 95 / 100) > Splitting the line like that makes it pretty hard to read. > > if (IS_BROADWELL(...) && > pipe_config->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) > > would look much better IMO. > >> + return false; >> + >> + return true; >> } >> >> -static void hsw_compute_ips_config(struct intel_crtc *crtc, >> - struct intel_crtc_state *pipe_config) >> +static bool hsw_compute_ips_config(struct intel_crtc_state *pipe_config) > s/pipe_config/crtc_state/ again > >> { >> - struct drm_device *dev = crtc->base.dev; >> - struct drm_i915_private *dev_priv = to_i915(dev); >> + struct drm_i915_private *dev_priv = >> + to_i915(pipe_config->base.crtc->dev); >> + struct intel_atomic_state *intel_state = >> + to_intel_atomic_state(pipe_config->base.state); >> + >> + if (!hsw_pipe_config_ips_capable(pipe_config)) >> + return false; >> + >> + if (pipe_config->ips_force_disable) >> + return false; >> + >> + /* >> + * FIXME IPS should be fine as long as one plane is >> + * enabled, but in practice it seems to have problems >> + * when going from primary only to sprite only and vice >> + * versa. >> + */ >> + if (!(pipe_config->active_planes & BIT(PLANE_PRIMARY))) >> + return false; >> >> - pipe_config->ips_enabled = i915_modparams.enable_ips && >> - hsw_crtc_supports_ips(crtc) && >> - pipe_config_supports_ips(dev_priv, pipe_config); >> + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ >> + if (IS_BROADWELL(dev_priv) && pipe_config->pixel_rate > >> + intel_state->cdclk.logical.cdclk * 95 / 100) >> + return false; > Another hard to read split. > > Apart from those nits, this lgtm so > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks, moved the split and did s/pipe_config/crtc_state/ (including on function name). Pushed.
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index e8884c2ade98..30affa7903d7 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1896,7 +1896,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate); /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) + if (IS_BROADWELL(dev_priv) && hsw_pipe_config_ips_capable(crtc_state)) min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 60d0a2d8534c..95df5c2128b4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -489,7 +489,7 @@ static const struct intel_limit intel_limits_bxt = { }; static bool -needs_modeset(struct drm_crtc_state *state) +needs_modeset(const struct drm_crtc_state *state) { return drm_atomic_crtc_needs_modeset(state); } @@ -4833,7 +4833,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - if (!crtc->config->ips_enabled) + if (!crtc_state->ips_enabled) return; /* @@ -4841,8 +4841,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) * This function is called from post_plane_update, which is run after * a vblank wait. */ - - assert_plane_enabled(to_intel_plane(crtc->base.primary)); + WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); if (IS_BROADWELL(dev_priv)) { mutex_lock(&dev_priv->pcu_lock); @@ -4877,8 +4876,6 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) if (!crtc_state->ips_enabled) return; - assert_plane_enabled(to_intel_plane(crtc->base.primary)); - if (IS_BROADWELL(dev_priv)) { mutex_lock(&dev_priv->pcu_lock); WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); @@ -4931,14 +4928,6 @@ intel_post_enable_primary(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_crtc->pipe; - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_enable_ips(new_crtc_state); - /* * Gen2 reports pipe underruns whenever all planes are disabled. * So don't enable underrun reporting before at least some planes @@ -4954,10 +4943,9 @@ intel_post_enable_primary(struct drm_crtc *crtc, intel_check_pch_fifo_underruns(dev_priv); } -/* FIXME move all this to pre_plane_update() with proper state tracking */ +/* FIXME get rid of this and use pre_plane_update */ static void -intel_pre_disable_primary(struct drm_crtc *crtc, - const struct intel_crtc_state *old_crtc_state) +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -4966,32 +4954,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc, /* * Gen2 reports pipe underruns whenever all planes are disabled. - * So diasble underrun reporting before all the planes get disabled. - * FIXME: Need to fix the logic to work when we turn off all planes - * but leave the pipe running. + * So disable underrun reporting before all the planes get disabled. */ if (IS_GEN2(dev_priv)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - /* - * FIXME IPS should be fine as long as one plane is - * enabled, but in practice it seems to have problems - * when going from primary only to sprite only and vice - * versa. - */ - hsw_disable_ips(old_crtc_state); -} - -/* FIXME get rid of this and use pre_plane_update */ -static void -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - int pipe = intel_crtc->pipe; - - intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state)); + hsw_disable_ips(to_intel_crtc_state(crtc->state)); /* * Vblank time updates from the shadow to live plane control register @@ -5007,6 +4975,38 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) intel_wait_for_vblank(dev_priv, pipe); } +static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!old_crtc_state->ips_enabled) + return false; + + if (needs_modeset(&new_crtc_state->base)) + return true; + + return !new_crtc_state->ips_enabled; +} + +static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->ips_enabled) + return false; + + if (needs_modeset(&new_crtc_state->base)) + return true; + + /* + * We can't read out IPS on broadwell, assume the worst and + * forcibly enable IPS on the first fastset. + */ + if (new_crtc_state->update_pipe && + old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED) + return true; + + return !old_crtc_state->ips_enabled; +} + static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); @@ -5023,6 +5023,9 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) if (pipe_config->update_wm_post && pipe_config->base.active) intel_update_watermarks(crtc); + if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) + hsw_enable_ips(pipe_config); + if (old_pri_state) { struct intel_plane_state *primary_state = intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), @@ -5053,6 +5056,9 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, struct intel_atomic_state *old_intel_state = to_intel_atomic_state(old_state); + if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) + hsw_disable_ips(old_crtc_state); + if (old_pri_state) { struct intel_plane_state *primary_state = intel_atomic_get_new_plane_state(old_intel_state, @@ -5061,10 +5067,13 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, to_intel_plane_state(old_pri_state); intel_fbc_pre_update(crtc, pipe_config, primary_state); - - if (old_primary_state->base.visible && + /* + * Gen2 reports pipe underruns whenever all planes are disabled. + * So disable underrun reporting before all the planes get disabled. + */ + if (IS_GEN2(dev_priv) && old_primary_state->base.visible && (modeset || !primary_state->base.visible)) - intel_pre_disable_primary(&crtc->base, old_crtc_state); + intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); } /* @@ -6195,18 +6204,20 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, return ret; } -static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, - struct intel_crtc_state *pipe_config) +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config) { - if (pipe_config->ips_force_disable) + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + /* IPS only exists on ULT machines and is tied to pipe A. */ + if (!hsw_crtc_supports_ips(crtc)) return false; - if (pipe_config->pipe_bpp > 24) + if (!i915_modparams.enable_ips) return false; - /* HSW can handle pixel rate up to cdclk? */ - if (IS_HASWELL(dev_priv)) - return true; + if (pipe_config->pipe_bpp > 24) + return false; /* * We compare against max which means we must take @@ -6215,19 +6226,41 @@ static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, * * Should measure whether using a lower cdclk w/o IPS */ - return pipe_config->pixel_rate <= - dev_priv->max_cdclk_freq * 95 / 100; + if (IS_BROADWELL(dev_priv) && pipe_config->pixel_rate > + dev_priv->max_cdclk_freq * 95 / 100) + return false; + + return true; } -static void hsw_compute_ips_config(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +static bool hsw_compute_ips_config(struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = + to_i915(pipe_config->base.crtc->dev); + struct intel_atomic_state *intel_state = + to_intel_atomic_state(pipe_config->base.state); + + if (!hsw_pipe_config_ips_capable(pipe_config)) + return false; + + if (pipe_config->ips_force_disable) + return false; + + /* + * FIXME IPS should be fine as long as one plane is + * enabled, but in practice it seems to have problems + * when going from primary only to sprite only and vice + * versa. + */ + if (!(pipe_config->active_planes & BIT(PLANE_PRIMARY))) + return false; - pipe_config->ips_enabled = i915_modparams.enable_ips && - hsw_crtc_supports_ips(crtc) && - pipe_config_supports_ips(dev_priv, pipe_config); + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ + if (IS_BROADWELL(dev_priv) && pipe_config->pixel_rate > + intel_state->cdclk.logical.cdclk * 95 / 100) + return false; + + return true; } static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) @@ -6345,9 +6378,6 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, intel_crtc_compute_pixel_rate(pipe_config); - if (HAS_IPS(dev_priv)) - hsw_compute_ips_config(crtc, pipe_config); - if (pipe_config->has_pch_encoder) return ironlake_fdi_compute_config(crtc, pipe_config); @@ -9183,6 +9213,19 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, ironlake_get_pfit_config(crtc, pipe_config); } + if (hsw_crtc_supports_ips(crtc)) { + if (IS_HASWELL(dev_priv)) + pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; + else { + /* + * We cannot readout IPS state on broadwell, set to + * true so we can set it to a defined state on first + * commit. + */ + pipe_config->ips_enabled = true; + } + } + if (pipe_config->cpu_transcoder != TRANSCODER_EDP && !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = @@ -10436,6 +10479,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, pipe_config); } + if (HAS_IPS(dev_priv)) + pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config); + return ret; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 635a96fcd788..4f4cf5128e0c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1485,6 +1485,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); bool intel_crtc_active(struct intel_crtc *crtc); +bool hsw_pipe_config_ips_capable(const struct intel_crtc_state *pipe_config); void hsw_enable_ips(const struct intel_crtc_state *crtc_state); void hsw_disable_ips(const struct intel_crtc_state *crtc_state); enum intel_display_power_domain intel_port_to_power_domain(enum port port); diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index 61641d479b93..1f5cd572a7ff 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -541,8 +541,6 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv, * completely disable it. */ pipe_config->ips_force_disable = enable; - if (pipe_config->ips_enabled == enable) - pipe_config->base.connectors_changed = true; } if (IS_HASWELL(dev_priv)) {
ips_enabled was used as a variable of whether IPS can be enabled or not, but should be used to test whether IPS is actually enabled. Changes since v1: - Call needs_modeset on new crtc state. (Ville) - IPS can be enabled with sprite plane enabled too. (Ville) - Fix CDCLK vs IPS workaround. (Ville) Changes since v2: - Only re-enable fastset when inheriting mode. (Ville) - Put the conditions for enabling and disabling IPS in a helper. Changes since v3: - Keep the max_cdclk workaround working. (Ville) - Also check logical cdclk out of paranoia. - Remove planes check from IPS disable function for initial disable. - Remove assert_plane_enabled/disabled checks and use crtc_state->active_planes for hsw_enable_ips only, always allow calling hsw_disable_ips to disable it initially in hw. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> --- drivers/gpu/drm/i915/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 168 ++++++++++++++++++++++------------ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pipe_crc.c | 2 - 4 files changed, 109 insertions(+), 64 deletions(-)