| Message ID | 20171125121230.23555-1-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Nov 25, 2017 at 8:12 PM, Andre Przywara <andre.przywara@arm.com> wrote: > To use pin PF4 as the RX signal of UART0, we have to write 0b011 into > the respective pin controller register. > Fix the wrong value we had in our table so far. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Fixes: 96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC") Acked-by: Chen-Yu Tsai <wens@csie.org>
On Sat, Nov 25, 2017 at 1:12 PM, Andre Przywara <andre.przywara@arm.com> wrote: > To use pin PF4 as the RX signal of UART0, we have to write 0b011 into > the respective pin controller register. > Fix the wrong value we had in our table so far. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Patch applied with Chen-Yu's ACK and fixes tag. Yours, Linus Walleij
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c index 4f2a726bbaeb..f5f77432ce6f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c @@ -428,7 +428,7 @@ static const struct sunxi_desc_pin a64_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"),
To use pin PF4 as the RX signal of UART0, we have to write 0b011 into the respective pin controller register. Fix the wrong value we had in our table so far. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)