From patchwork Mon Dec 4 12:53:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C5=81ukasz_Stelmach?= X-Patchwork-Id: 10090199 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D8C5A60327 for ; Mon, 4 Dec 2017 12:54:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 00F7228EBA for ; Mon, 4 Dec 2017 12:54:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E9ADF2916B; Mon, 4 Dec 2017 12:54:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 45F8228EBA for ; Mon, 4 Dec 2017 12:54:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753913AbdLDMy3 (ORCPT ); Mon, 4 Dec 2017 07:54:29 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:48192 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751821AbdLDMyT (ORCPT ); Mon, 4 Dec 2017 07:54:19 -0500 Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20171204125416euoutp02cd8ab672c2fe8a9b9fc7571f7f90843b~9GJAV_RHu0163201632euoutp02G; Mon, 4 Dec 2017 12:54:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20171204125416euoutp02cd8ab672c2fe8a9b9fc7571f7f90843b~9GJAV_RHu0163201632euoutp02G DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1512392057; bh=Y1jLyD+1RfdGyGB0CUHF1DqYwXKTpuB+3tGo9E66hl4=; h=From:To:Cc:Subject:Date:In-reply-to:In-reply-to:References:From; b=a0P6T0dWH3rhi03o0NoOsL7Mmbx+GGzJHgMU6/hBeJVN8Nto096YKUqlnR3l4+iCD 1/LgJxYlGCkaF9p5YR/NAfJTu0UqmWlZwVkOa0cAeoC9BAAgfkUNRdQrFVOy1c/jBY Fqg0GD7iKrzWZkBnSEfEiFui9O4Fd6I0zv824L7g= Received: from eusmges2.samsung.com (unknown [203.254.199.241]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20171204125416eucas1p1d3719b40c7b64d6aeddfe00e9f6b08e1~9GI-fW8xJ1140111401eucas1p1q; Mon, 4 Dec 2017 12:54:16 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges2.samsung.com (EUCPMTA) with SMTP id 38.26.12907.775452A5; Mon, 4 Dec 2017 12:54:15 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20171204125415eucas1p1f94e6996f08938f686c08c00247c62ce~9GI_ylXCD1142111421eucas1p1g; Mon, 4 Dec 2017 12:54:15 +0000 (GMT) X-AuditID: cbfec7f1-f793a6d00000326b-0d-5a2545777a83 Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 49.C2.20118.775452A5; Mon, 4 Dec 2017 12:54:15 +0000 (GMT) MIME-version: 1.0 Content-transfer-encoding: 8BIT Content-type: text/plain; charset="UTF-8" Received: from localhost ([106.116.147.110]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P0F00CVST6FU240@eusync2.samsung.com>; Mon, 04 Dec 2017 12:54:15 +0000 (GMT) From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= To: "Andrew F . Davis" , PrasannaKumar Muralidharan , Rob Herring , Matt Mackall , Herbert Xu , Krzysztof Kozlowski , Kukjin Kim , devicetree@vger.kernel.org, linux-crypto@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?=C5=81ukasz=20Stelmach?= , Marek Szyprowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 2/3] hwrng: exynos - add Samsung Exynos True RNG driver Date: Mon, 04 Dec 2017 13:53:50 +0100 Message-id: <20171204125351.26805-3-l.stelmach@samsung.com> X-Mailer: git-send-email 2.11.0 In-reply-to: <20171204125351.26805-1-l.stelmach@samsung.com> In-reply-to: <20171204120429.22892-1-l.stelmach@samsung.com> Organization: Samsung R&D Institute Poland X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJKsWRmVeSWpSXmKPExsWy7djPc7rlrqpRBk97DC3en5rIbrFxxnpW i/lHzrFadL+Sseh//JrZ4vz5DewWNw+tYLS4f+8nk8XlXXPYLGac38dksfbIXXaLBdv6GC2W 9h9ntGjde4Tdgc9j56y77B7bDqh6bFrVyebRt2UVo0ffyw2MHsdvbGfy+LxJLoA9issmJTUn syy1SN8ugStjwuo7jAXz3SsunnnH0sC40aqLkZNDQsBE4tStP8wQtpjEhXvr2boYuTiEBJYy Spx/0cIK4XxmlDg86RkTTMfLNXeZIBLLGCWO9E4Aa+cVEJT4MfkeSxcjBwezgLzEkUvZIGFm AU2JrbvXs4PYQgJfGCWeTJAAsdkEHCX6l54AWyAiMJlZ4s6ed+wgDjPI0IPbTrKBVAkLeEm8 OjIPrJtFQFVi5trtUMusJZZMmgx1t7zErraLrCA2p4CNxMP2zSww9vxZl8Hm8AtoSaxpus4C skBCYBW7xIZp26DecZHoa2mGGiQs8er4FnYIW0bi8uRuqIZ+oP/nf4dKTGGUWLzQAcK2lviz aiIbxJ98EpO2TWcGeV9CgFeio00IosRD4u/URhYI21Fi/66ZzJCgA5o5eXsH+wRGhVlIoTcL EXqzkEJvASPzKkaR1NLi3PTUYiO94sTc4tK8dL3k/NxNjMAEdvrf8Y87GN+fsDrEKMDBqMTD q5CoEiXEmlhWXJl7iFGCg1lJhNdTXzVKiDclsbIqtSg/vqg0J7X4EKM0B4uSOK9tVFukkEB6 YklqdmpqQWoRTJaJg1OqgbG+6f3LGNYp93zV+/c3xK7YK+R78XiV+NGYvq9hrDPdZ/4UeBNi fzpJLjpj744/ulsD+ip1mZ9IMQr7FLSmbz3c19xkq6542XNxmYG944+5Zo/VVY7WzVaJv7I/ 0aavdbL1fGmld6HnuHUTn3Qqp35lPCz98fvqw1yhYbn+oeJsre+lZnRXKLEUZyQaajEXFScC AJD4u55cAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJIsWRmVeSWpSXmKPExsVy+t/xK7rlrqpRBlcmCFm8PzWR3WLjjPWs FvOPnGO16H4lY9H/+DWzxfnzG9gtbh5awWhx/95PJovLu+awWcw4v4/JYu2Ru+wWC7b1MVos 7T/OaNG69wi7A5/Hzll32T22HVD12LSqk82jb8sqRo++lxsYPY7f2M7k8XmTXAB7FJdNSmpO Zllqkb5dAlfGhNV3GAvmu1dcPPOOpYFxo1UXIyeHhICJxMs1d5kgbDGJC/fWs4HYQgJLGCWu zLYAsXkFBCV+TL7H0sXIwcEsIC9x5FI2SJhZQF1i0rxFzF2MXEDl3xglbqxeywKSYBNwlOhf eoIVJCEiMJVZ4n9bF5jDLLCMUeJPTyvYBmEBL4lXR+axg9gsAqoSM9duZ4bYZi2xZNJkZoiL 5CV2tV1kBbE5BWwkHrZvZoG4zlri4fEuJpj4/FmX2WDiXa0vwXr5BbQk1jRdZ5nAKDwLyROz EJ6YheSJBYzMqxhFUkuLc9Nzi430ihNzi0vz0vWS83M3MQIjcNuxn1t2MHa9Cz7EKMDBqMTD q5CoEiXEmlhWXJl7iFGCg1lJhNdTXzVKiDclsbIqtSg/vqg0J7X4EKM0B4uSOG/vntWRQgLp iSWp2ampBalFMFkmDk6pBsacL5Gm5zoPfQ5fF/77wB45ce6JTyN367JfaFvLlx/8YqbzpFBT /+qeG1PnB4V9jO+yc1hh9uzYzIKJwcbZE80Dequ+zvDy3RG026u3+P7a3UmtzeqJQlp+rFzv 7bonTPjkFr2Do7XlVMuRlT9P6BeYnVBYvaLewvOc8xTBVWKZOzKYtJc9VlViKc5INNRiLipO BABnwtTivAIAAA== X-CMS-MailID: 20171204125415eucas1p1f94e6996f08938f686c08c00247c62ce X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20171204125415eucas1p1f94e6996f08938f686c08c00247c62ce X-RootMTR: 20171204125415eucas1p1f94e6996f08938f686c08c00247c62ce References: <20171204125351.26805-1-l.stelmach@samsung.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for True Random Number Generator found in Samsung Exynos 5250+ SoCs. Signed-off-by: Łukasz Stelmach Reviewed-by: Krzysztof Kozlowski --- MAINTAINERS | 7 + drivers/char/hw_random/Kconfig | 12 ++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/exynos-trng.c | 245 +++++++++++++++++++++++++++++++++++ 4 files changed, 265 insertions(+) create mode 100644 drivers/char/hw_random/exynos-trng.c diff --git a/MAINTAINERS b/MAINTAINERS index 2811a211632c..992074cca612 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11780,6 +11780,13 @@ S: Maintained F: drivers/crypto/exynos-rng.c F: Documentation/devicetree/bindings/rng/samsung,exynos-rng4.txt +SAMSUNG EXYNOS TRUE RANDOM NUMBER GENERATOR (TRNG) DRIVER +M: Łukasz Stelmach +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/char/hw_random/exynos-trng.c +F: Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.txt + SAMSUNG FRAMEBUFFER DRIVER M: Jingoo Han L: linux-fbdev@vger.kernel.org diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 95a031e9eced..292e6b36d493 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -449,6 +449,18 @@ config HW_RANDOM_S390 If unsure, say Y. +config HW_RANDOM_EXYNOS + tristate "Samsung Exynos True Random Number Generator support" + depends on ARCH_EXYNOS || COMPILE_TEST + default HW_RANDOM + ---help--- + This driver provides support for the True Random Number + Generator available in Exynos SoCs. + + To compile this driver as a module, choose M here: the module + will be called exynos-trng. + + If unsure, say Y. endif # HW_RANDOM config UML_RANDOM diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index f3728d008fff..5595df97da7a 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o n2-rng-y := n2-drv.o n2-asm.o obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o +obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-trng.o obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o obj-$(CONFIG_HW_RANDOM_OMAP3_ROM) += omap3-rom-rng.o diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c new file mode 100644 index 000000000000..971d2fe9d55a --- /dev/null +++ b/drivers/char/hw_random/exynos-trng.c @@ -0,0 +1,245 @@ +/* + * RNG driver for Exynos TRNGs + * + * Author: Łukasz Stelmach + * + * Copyright 2017 (c) Samsung Electronics Software, Inc. + * + * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by + * Krzysztof Kozłowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EXYNOS_TRNG_CLKDIV (0x0) + +#define EXYNOS_TRNG_CTRL (0x20) +#define EXYNOS_TRNG_CTRL_RNGEN BIT(31) + +#define EXYNOS_TRNG_POST_CTRL (0x30) +#define EXYNOS_TRNG_ONLINE_CTRL (0x40) +#define EXYNOS_TRNG_ONLINE_STAT (0x44) +#define EXYNOS_TRNG_ONLINE_MAXCHI2 (0x48) +#define EXYNOS_TRNG_FIFO_CTRL (0x50) +#define EXYNOS_TRNG_FIFO_0 (0x80) +#define EXYNOS_TRNG_FIFO_1 (0x84) +#define EXYNOS_TRNG_FIFO_2 (0x88) +#define EXYNOS_TRNG_FIFO_3 (0x8c) +#define EXYNOS_TRNG_FIFO_4 (0x90) +#define EXYNOS_TRNG_FIFO_5 (0x94) +#define EXYNOS_TRNG_FIFO_6 (0x98) +#define EXYNOS_TRNG_FIFO_7 (0x9c) +#define EXYNOS_TRNG_FIFO_LEN (8) +#define EXYNOS_TRNG_CLOCK_RATE (500000) + + +struct exynos_trng_dev { + struct device *dev; + void __iomem *mem; + struct clk *clk; + struct hwrng rng; +}; + +static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max, + bool wait) +{ + struct exynos_trng_dev *trng; + u32 val; + + max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4)); + + trng = (struct exynos_trng_dev *)rng->priv; + + writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL); + val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val, + val == 0, 200, 1000000); + if (val < 0) + return val; + + memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max); + + return max; +} + +static int exynos_trng_init(struct hwrng *rng) +{ + struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; + unsigned long sss_rate; + u32 val; + + sss_rate = clk_get_rate(trng->clk); + + /* + * For most TRNG circuits the clock frequency of under 500 kHz + * is safe. + */ + val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2); + if (val > 0x7fff) { + dev_err(trng->dev, "clock divider too large: %d", val); + return -ERANGE; + } + val = val << 1; + writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV); + + /* Enable the generator. */ + val = EXYNOS_TRNG_CTRL_RNGEN; + writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL); + + /* + * Disable post-processing. /dev/hwrng is supposed to deliver + * unprocessed data. + */ + writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL); + + return 0; +} + +static int exynos_trng_probe(struct platform_device *pdev) +{ + struct exynos_trng_dev *trng; + struct resource *res; + int ret = -ENOMEM; + + trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL); + if (!trng) + return ret; + + trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev), + GFP_KERNEL); + if (!trng->rng.name) + return ret; + + trng->rng.init = exynos_trng_init; + trng->rng.read = exynos_trng_do_read; + trng->rng.priv = (unsigned long) trng; + + platform_set_drvdata(pdev, trng); + trng->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + trng->mem = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(trng->mem)) { + dev_err(&pdev->dev, "Could not map IO resources.\n"); + return PTR_ERR(trng->mem); + } + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "Could not get runtime PM.\n"); + goto err_pm_get; + } + + trng->clk = devm_clk_get(&pdev->dev, "secss"); + if (IS_ERR(trng->clk)) { + ret = PTR_ERR(trng->clk); + dev_err(&pdev->dev, "Could not get clock.\n"); + goto err_clock; + } + + ret = clk_prepare_enable(trng->clk); + if (ret) { + dev_err(&pdev->dev, "Could not enable the clk.\n"); + goto err_clock; + } + + ret = hwrng_register(&trng->rng); + if (ret) { + dev_err(&pdev->dev, "Could not register hwrng device.\n"); + goto err_register; + } + + dev_info(&pdev->dev, "Exynos True Random Number Generator.\n"); + + return 0; + +err_register: + clk_disable_unprepare(trng->clk); + +err_clock: + pm_runtime_put_sync(&pdev->dev); + +err_pm_get: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int exynos_trng_remove(struct platform_device *pdev) +{ + struct exynos_trng_dev *trng = platform_get_drvdata(pdev); + + hwrng_unregister(&trng->rng); + clk_disable_unprepare(trng->clk); + + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused exynos_trng_suspend(struct device *dev) +{ + pm_runtime_put_sync(dev); + + return 0; +} + +static int __maybe_unused exynos_trng_resume(struct device *dev) +{ + int ret; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Could not get runtime PM.\n"); + pm_runtime_put_noidle(dev); + return ret; + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend, + exynos_trng_resume); + +static const struct of_device_id exynos_trng_dt_match[] = { + { + .compatible = "samsung,exynos5250-trng", + }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos_rng_dt_match); + +static struct platform_driver exynos_trng_driver = { + .driver = { + .name = "exynos-trng", + .pm = &exynos_trng_pm_ops, + .of_match_table = exynos_trng_dt_match, + }, + .probe = exynos_trng_probe, + .remove = exynos_trng_remove, +}; + +module_platform_driver(exynos_trng_driver); +MODULE_AUTHOR("Łukasz Stelmach"); +MODULE_DESCRIPTION("H/W TRNG driver for Exynos chips"); +MODULE_LICENSE("GPL");