From patchwork Thu Dec 7 00:00:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10097451 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CD59860360 for ; Thu, 7 Dec 2017 00:01:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCBC72A17E for ; Thu, 7 Dec 2017 00:01:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B14752A181; Thu, 7 Dec 2017 00:01:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 327A92A188 for ; Thu, 7 Dec 2017 00:01:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 37D416E771; Thu, 7 Dec 2017 00:00:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yb0-x242.google.com (mail-yb0-x242.google.com [IPv6:2607:f8b0:4002:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 179EB6E770 for ; Thu, 7 Dec 2017 00:00:57 +0000 (UTC) Received: by mail-yb0-x242.google.com with SMTP id t127so2294692ybf.9 for ; Wed, 06 Dec 2017 16:00:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HpJYJRv+GHb+RvfleeHKeK1IHjUJlBHKADmsQIS7oW4=; b=QYZOE7BKZiUD1h2GcjsLXTvCTXbIeX+XXG/xcbB4/WvWI2OLq3fKNekZ3JvvQp/sXG 3+RG+D36bix5Xy8ggubo1xp2PTN4PF10fzKb+3q0bFBd1x33Pt6v1+S/bb+a7I5Sxvmf rRzatoWdl4aoNe8vorMbagt40a4em9bfyuRnY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HpJYJRv+GHb+RvfleeHKeK1IHjUJlBHKADmsQIS7oW4=; b=pnxbU/4AKxVcBPvoIOfS+2uDCA0XfzSIZ8VsEM77vkWmqE4aV2KMJqEwqV9yuxzaIY F7cRdx07VqnDX3XbbySgEdn0Ef/zGhPJTFrVScy5DjnIzWKqjGoJdbTFNjNY4qaImHzw 1Ltv73Vk6nNBvp8ylnKSjED4aqqzDDTwSt/ML22pbDe16kGAlbcNoI8Qg/bLgKFhWOAD +QUEUbSeKrn0hgYKI0hb7IFYAzcfUeLBwf1wRy9+1Duok/sxns55IFABpLp8XhX7VkDs UoC05W2AMmwZo8ynnz6sXW/4ZBR9ktsrtTKZ4bVDjPYmQXP55HQOqllqhnI4RLIp9HzS ezFA== X-Gm-Message-State: AJaThX7xwXXwIqD/GfyLg60NOzo8MCWLkmjl1rcl5Mdf6KJ0/IYtMnid sPZk0hserVKf2HgGhVghKcXZUQ== X-Google-Smtp-Source: AGs4zMYbYtUQ/nN7tsp1QsSlO2gKJyr+E4iXuWmSBIeogptJTAXSFgk3MEn7FMj1UsWykYbe4OKQ+A== X-Received: by 10.37.179.66 with SMTP id k2mr16452980ybg.53.1512604856285; Wed, 06 Dec 2017 16:00:56 -0800 (PST) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:d3af:69ac:1964:28e8]) by smtp.gmail.com with ESMTPSA id l21sm1852412ywc.34.2017.12.06.16.00.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Dec 2017 16:00:55 -0800 (PST) From: Sean Paul To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Wed, 6 Dec 2017 19:00:09 -0500 Message-Id: <20171207000014.10083-7-seanpaul@chromium.org> X-Mailer: git-send-email 2.15.1.424.g9478a66081-goog In-Reply-To: <20171207000014.10083-1-seanpaul@chromium.org> References: <20171207000014.10083-1-seanpaul@chromium.org> MIME-Version: 1.0 Cc: seanpaul@google.com, David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org, Rodrigo Vivi , daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH v4 6/9] drm/i915: Make use of indexed write GMBUS feature X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch enables the indexed write feature of the GMBUS to concatenate 2 consecutive messages into one. The criteria for an indexed write is that both messages are writes, the first is length == 1, and the second is length > 0. The first message is sent out by the GMBUS as the slave command, and the second one is sent via the GMBUS FIFO as usual. Changes in v3: - Added to series Changes in v4: - Combine indexed reads and writes (Ville) Cc: Daniel Vetter Suggested-by: Ville Syrjälä Signed-off-by: Sean Paul Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_i2c.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 49fdf09f9919..d78ce758fbfa 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -373,7 +373,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, static int gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, - unsigned short addr, u8 *buf, unsigned int len) + unsigned short addr, u8 *buf, unsigned int len, + u32 gmbus1_index) { unsigned int chunk_size = len; u32 val, loop; @@ -386,7 +387,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, I915_WRITE_FW(GMBUS3, val); I915_WRITE_FW(GMBUS1, - GMBUS_CYCLE_WAIT | + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); @@ -409,7 +410,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, } static int -gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) +gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, + u32 gmbus1_index) { u8 *buf = msg->buf; unsigned int tx_size = msg->len; @@ -419,7 +421,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) do { len = min(tx_size, GMBUS_BYTE_COUNT_MAX); - ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); + ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, + gmbus1_index); if (ret) return ret; @@ -431,21 +434,21 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) } /* - * The gmbus controller can combine a 1 or 2 byte write with a read that - * immediately follows it by using an "INDEX" cycle. + * The gmbus controller can combine a 1 or 2 byte write with another read/write + * that immediately follows it by using an "INDEX" cycle. */ static bool -gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) +gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) { return (i + 1 < num && msgs[i].addr == msgs[i + 1].addr && !(msgs[i].flags & I2C_M_RD) && (msgs[i].len == 1 || msgs[i].len == 2) && - (msgs[i + 1].flags & I2C_M_RD)); + msgs[i + 1].len > 0); } static int -gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) +gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) { u32 gmbus1_index = 0; u32 gmbus5 = 0; @@ -462,7 +465,10 @@ gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) if (gmbus5) I915_WRITE_FW(GMBUS5, gmbus5); - ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); + if (msgs[1].flags & I2C_M_RD) + ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); + else + ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); /* Clear GMBUS5 after each index transfer */ if (gmbus5) @@ -486,13 +492,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) for (; i < num; i += inc) { inc = 1; - if (gmbus_is_index_read(msgs, i, num)) { - ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); - inc = 2; /* an index read is two msgs */ + if (gmbus_is_index_xfer(msgs, i, num)) { + ret = gmbus_index_xfer(dev_priv, &msgs[i]); + inc = 2; /* an index transmission is two msgs */ } else if (msgs[i].flags & I2C_M_RD) { ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); } else { - ret = gmbus_xfer_write(dev_priv, &msgs[i]); + ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); } if (!ret)