From patchwork Tue Dec 19 09:45:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 10122891 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9A228603B5 for ; Tue, 19 Dec 2017 09:46:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C951291CB for ; Tue, 19 Dec 2017 09:46:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 81019291CD; Tue, 19 Dec 2017 09:46:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 08EDF291CB for ; Tue, 19 Dec 2017 09:46:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966912AbdLSJqE (ORCPT ); Tue, 19 Dec 2017 04:46:04 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:18110 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030236AbdLSJp5 (ORCPT ); Tue, 19 Dec 2017 04:45:57 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9jrbJ027611; Tue, 19 Dec 2017 03:45:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513676753; bh=ZEl50q124V+QV2kE9zTa+B6lIgJ8WYEmsu+H98q6rkw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LtJbS9/DUhv2PoVtN7v5d/FzUhpVmUgKiamf839HmzRtsr80fxKc6hF91Ry1LemzD siYsfDK7WoMJf6Djd67zpba+cGjvHuvwLEAAu/tSdXuRbqxUdK9ncwSm69Jpi+UZLj daLxCOFxqUbZ5AJknzLcMhC6sF+mfOGD9PGxCgc0= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9jrS0005243; Tue, 19 Dec 2017 03:45:53 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:45:52 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:45:53 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9jk2i028458; Tue, 19 Dec 2017 03:45:50 -0600 From: Kishon Vijay Abraham I To: Rob Herring , Mark Rutland , CC: , , , Subject: [PATCH 1/2] dt-bindings: phy: ti-pipe3: Add dt binding to use USB3 PHY for PCIe Date: Tue, 19 Dec 2017 15:15:39 +0530 Message-ID: <20171219094540.18432-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219094540.18432-1-kishon@ti.com> References: <20171219094540.18432-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property to indicate if the USB3 PHY should be used for 2nd lane of PCIe. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index cd13e6157088..907a046e794b 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -93,6 +93,8 @@ Optional properties: register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. - syscon-pcs : phandle/offset pair. Phandle to the system control module and the register offset to write the PCS delay value. + - "ti,configure-as-pcie" : property to indicate if the PHY should be + configured as PCIE PHY. Deprecated properties: - ctrl-module : phandle of the control module used by PHY driver to power on