From patchwork Thu Jul 28 06:41:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1014542 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6S6nuqo023086 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 28 Jul 2011 06:50:17 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QmKPh-0001Ag-Dt; Thu, 28 Jul 2011 06:49:46 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QmKPg-0006cS-MQ; Thu, 28 Jul 2011 06:49:44 +0000 Received: from dakia2.marvell.com ([65.219.4.35]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QmKPI-0006XP-RQ for linux-arm-kernel@lists.infradead.org; Thu, 28 Jul 2011 06:49:22 +0000 X-ASG-Debug-ID: 1311835758-082befb70001-tbGyMd Received: from maili.marvell.com (maili.marvell.com [10.68.76.51]) by dakia2.marvell.com with ESMTP id ajQn81KGktdrJX5I; Wed, 27 Jul 2011 23:49:18 -0700 (PDT) X-Barracuda-Envelope-From: haojian.zhuang@marvell.com Received: from localhost (unknown [10.38.164.65]) by maili.marvell.com (Postfix) with ESMTP id 9C9848A002; Wed, 27 Jul 2011 23:49:17 -0700 (PDT) From: Haojian Zhuang To: haojian.zhuang@gmail.com, eric.y.miao@gmail.com, linux@arm.linux.org.uk, grant.likely@secretlab.ca, alan@linux.intel.com, linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org X-ASG-Orig-Subj: [PATCH v2 2/7] ARM: mmp: parse timer configuration from DT Subject: [PATCH v2 2/7] ARM: mmp: parse timer configuration from DT Date: Thu, 28 Jul 2011 14:41:28 +0800 X-ASG-Orig-Subj: [PATCH v2 2/7] ARM: mmp: parse timer configuration from DT Message-Id: <1311835293-18125-3-git-send-email-haojian.zhuang@marvell.com> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1311835293-18125-2-git-send-email-haojian.zhuang@marvell.com> References: <1311835293-18125-1-git-send-email-haojian.zhuang@marvell.com> <1311835293-18125-2-git-send-email-haojian.zhuang@marvell.com> X-Barracuda-Connect: maili.marvell.com[10.68.76.51] X-Barracuda-Start-Time: 1311835758 X-Barracuda-URL: http://10.68.76.222:80/cgi-mod/mark.cgi X-Barracuda-Spam-Score: -1002.00 X-Barracuda-Spam-Status: No, SCORE=-1002.00 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=1000.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110728_024921_078361_2E848578 X-CRM114-Status: GOOD ( 18.53 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.2 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Thu, 28 Jul 2011 06:50:17 +0000 (UTC) Parse timer configuration from DT. Now we can merge pxa910_timer and mmp2_timer into mmp_timer. Since most configuration between these two timers are same. The difference is recorded in DT. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/arm/marvell/timer.txt | 24 +++++++++ arch/arm/mach-mmp/common.h | 2 + arch/arm/mach-mmp/time.c | 50 +++++++++++++++++++- 3 files changed, 75 insertions(+), 1 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/marvell/timer.txt diff --git a/Documentation/devicetree/bindings/arm/marvell/timer.txt b/Documentation/devicetree/bindings/arm/marvell/timer.txt new file mode 100644 index 0000000..24a6f97 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/timer.txt @@ -0,0 +1,24 @@ +* Timer Controller Binding for ARCH-MMP + +This binding specifies what properties must be available in device tree +representation of an ARCH-MMP compliant timer controller. + +Required properties: + + - compatible: Specifies the compatibility list of the timer controller. + The type shall be and the value shall be + "mrvl,pxa168-timer". + + - mrvl,clk-conf: Specifies the address and value of timer + configuration register. + The type shall be . The first value indicates + the physical address of timer configuration register. The second + value indicates data should be written to timer configuration + register. + +* Example + + mmp_timer: { + compatible = "mrvl,pxa168-timer"; + mrvl,clk-conf = <0xd4000034 0x33>; + }; diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index 1c563c2..890c664 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -2,6 +2,8 @@ struct sys_timer; +extern struct sys_timer mmp_timer; + extern void timer_init(int irq); extern void __init icu_init_irq(void); diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 99833b9..5a90b27 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -25,6 +25,8 @@ #include #include +#include +#include #include #include @@ -150,7 +152,7 @@ static void __init timer_config(void) __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ - ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3); + ccr &= TMR_CCR_CS_0(0); __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); /* free-running mode */ @@ -187,3 +189,49 @@ void __init timer_init(int irq) clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); clockevents_register_device(&ckevt); } + +#ifdef CONFIG_OF +static void __init mmp_timer_init(void) +{ + struct device_node *np; + const __be32 *clk_offs; + void __iomem *conf; + unsigned int addr = 0, offs = 0; + int size, irq; + + np = of_find_compatible_node(NULL, NULL, "mrvl,pxa168-timer"); + + BUG_ON(!np); + + of_node_get(np); + irq = irq_of_parse_and_map(np, 0); + + clk_offs = of_get_property(np, "mrvl,clk-conf", &size); + if ((clk_offs == NULL) || (size != sizeof(int) * 2)) { + pr_warn("mmp-timer: mrvl,clk-conf property is wrong\n"); + goto out; + } + addr = be32_to_cpu(*clk_offs) & PAGE_MASK; + offs = be32_to_cpu(*clk_offs) - addr; + conf = ioremap(addr, PAGE_SIZE); + if (conf == NULL) { + pr_warn("mmp-timer: failed on mapping 0x%x\n", (uint32_t)conf); + goto out; + } + /* reset and configure */ + __raw_writel(APBC_APBCLK | APBC_RST, conf + offs); + __raw_writel(be32_to_cpu(*++clk_offs), conf + offs); + __raw_readl(conf + offs); + iounmap(conf); + + timer_init(irq); + return; +out: + of_node_put(np); + return; +} + +struct sys_timer mmp_timer = { + .init = mmp_timer_init, +}; +#endif