Patchwork [v2] PCI: dwc: fix enumeration end when reaching root subordinate

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Submitter Koen Vandeputte
Date Jan. 15, 2018, 9:36 a.m.
Message ID <1516008968-26285-1-git-send-email-koen.vandeputte@ncentric.com>
Download mbox | patch
Permalink /patch/10163363/
State New
Headers show

Comments

Koen Vandeputte - Jan. 15, 2018, 9:36 a.m.
The subordinate value indicates the highest bus number which can be
reached downstream though a certain device.

Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
parent")
ensures that downstream devices cannot assign busnumbers higher than the
upstream device subordinate number, which was indeed illogical.

By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
value of 0x01.

Due to this combined with above commit, enumeration stops digging deeper
downstream as soon as bus num 0x01 has been assigned, which is always
the case for a bridge device.

This results in all devices behind a bridge bus to remain undetected, as
these would be connected to bus 0x02 or higher.

Fix this by initializing the RC to a subordinate value of 0xff, which is
not altering hardware behaviour in any way, but informs probing
function pci_scan_bridge() later on which reads this value back from
register.

Following nasty errors during boot are also fixed by this:

[    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
under [bus 01] (conflicts with (null) [bus 01])
...
[    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
0000:01 [bus 01]
...
[    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
0000:01 [bus 01]
...
[    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
0000:01 [bus 01]
[    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
05
[    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
under [bus 01] (conflicts with (null) [bus 01])
[    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
bridge 0000:01 [bus 01]

Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
parent")
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Tested-by: Niklas Cassel <niklas.cassel@axis.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Jianguo Sun <sunjianguo1@huawei.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Minghuan Lian <minghuan.Lian@freescale.com>
Cc: Mingkai Hu <mingkai.hu@freescale.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
---
 drivers/pci/dwc/pcie-designware-host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Mason - Jan. 15, 2018, 11:50 a.m.
On 15/01/2018 10:36, Koen Vandeputte wrote:

> The subordinate value indicates the highest bus number which can be
> reached downstream though a certain device.
> 
> Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> parent")
> ensures that downstream devices cannot assign busnumbers higher than the
> upstream device subordinate number, which was indeed illogical.
> 
> By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
> value of 0x01.
> 
> Due to this combined with above commit, enumeration stops digging deeper
> downstream as soon as bus num 0x01 has been assigned, which is always
> the case for a bridge device.
> 
> This results in all devices behind a bridge bus to remain undetected, as
> these would be connected to bus 0x02 or higher.
> 
> Fix this by initializing the RC to a subordinate value of 0xff, which is
> not altering hardware behaviour in any way, but informs probing
> function pci_scan_bridge() later on which reads this value back from
> register.
> 
> Following nasty errors during boot are also fixed by this:
> 
> [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
> under [bus 01] (conflicts with (null) [bus 01])
> ...
> [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
> 0000:01 [bus 01]
> [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
> 05
> [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
> under [bus 01] (conflicts with (null) [bus 01])
> [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
> bridge 0000:01 [bus 01]

FWIW, I find that this wrap-around looks ugly :-p

Regards.
Fabio Estevam - Jan. 15, 2018, 7:47 p.m.
Hi Koen,

On Mon, Jan 15, 2018 at 7:36 AM, Koen Vandeputte
<koen.vandeputte@ncentric.com> wrote:
> The subordinate value indicates the highest bus number which can be
> reached downstream though a certain device.
>
> Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> parent")
> ensures that downstream devices cannot assign busnumbers higher than the
> upstream device subordinate number, which was indeed illogical.
>
> By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
> value of 0x01.
>
> Due to this combined with above commit, enumeration stops digging deeper
> downstream as soon as bus num 0x01 has been assigned, which is always
> the case for a bridge device.
>
> This results in all devices behind a bridge bus to remain undetected, as
> these would be connected to bus 0x02 or higher.
>
> Fix this by initializing the RC to a subordinate value of 0xff, which is
> not altering hardware behaviour in any way, but informs probing
> function pci_scan_bridge() later on which reads this value back from
> register.
>
> Following nasty errors during boot are also fixed by this:
>
> [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
> under [bus 01] (conflicts with (null) [bus 01])
> ...
> [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
> 0000:01 [bus 01]
> [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
> 05
> [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
> under [bus 01] (conflicts with (null) [bus 01])
> [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
> bridge 0000:01 [bus 01]
>
> Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> parent")
> Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
> Tested-by: Niklas Cassel <niklas.cassel@axis.com>
> Cc: Binghui Wang <wangbinghui@hisilicon.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Jianguo Sun <sunjianguo1@huawei.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
> Cc: Minghuan Lian <minghuan.Lian@freescale.com>
> Cc: Mingkai Hu <mingkai.hu@freescale.com>
> Cc: Murali Karicheri <m-karicheri2@ti.com>
> Cc: Pratyush Anand <pratyush.anand@gmail.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Roy Zang <tie-fei.zang@freescale.com>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Xiaowei Song <songxiaowei@hisilicon.com>
> Cc: Zhou Wang <wangzhou1@hisilicon.com>

This fixes Intel Wifi card detection via bridge.

I adapted it to kernel 4.9 and it worked fine, so:

Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

Kernel 4.9 does not contain a20c7f36bd3d ("PCI: Do not allocate more
buses than available in parent"), so it seems the commit log needs to
be reworded for the older kernels.

Thanks
Mika Westerberg - Jan. 15, 2018, 7:52 p.m.
On Mon, Jan 15, 2018 at 10:36:08AM +0100, Koen Vandeputte wrote:
> The subordinate value indicates the highest bus number which can be
> reached downstream though a certain device.
> 
> Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> parent")
> ensures that downstream devices cannot assign busnumbers higher than the
> upstream device subordinate number, which was indeed illogical.
> 
> By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
> value of 0x01.
> 
> Due to this combined with above commit, enumeration stops digging deeper
> downstream as soon as bus num 0x01 has been assigned, which is always
> the case for a bridge device.
> 
> This results in all devices behind a bridge bus to remain undetected, as
> these would be connected to bus 0x02 or higher.
> 
> Fix this by initializing the RC to a subordinate value of 0xff, which is
> not altering hardware behaviour in any way, but informs probing
> function pci_scan_bridge() later on which reads this value back from
> register.
> 
> Following nasty errors during boot are also fixed by this:
> 
> [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
> under [bus 01] (conflicts with (null) [bus 01])
> ...
> [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
> 0000:01 [bus 01]
> [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
> 05
> [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
> under [bus 01] (conflicts with (null) [bus 01])
> [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
> bridge 0000:01 [bus 01]
> 
> Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> parent")
> Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
> Tested-by: Niklas Cassel <niklas.cassel@axis.com>
> Cc: Binghui Wang <wangbinghui@hisilicon.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Jianguo Sun <sunjianguo1@huawei.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Mika Westerberg <mika.westerberg@linux.intel.com>

Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Lorenzo Pieralisi - Feb. 5, 2018, 7:14 p.m.
On Mon, Jan 15, 2018 at 10:36:08AM +0100, Koen Vandeputte wrote:
> The subordinate value indicates the highest bus number which can be
> reached downstream though a certain device.
> 
> Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> parent")
> ensures that downstream devices cannot assign busnumbers higher than the
> upstream device subordinate number, which was indeed illogical.
> 
> By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
> value of 0x01.
> 
> Due to this combined with above commit, enumeration stops digging deeper
> downstream as soon as bus num 0x01 has been assigned, which is always
> the case for a bridge device.
> 
> This results in all devices behind a bridge bus to remain undetected, as
> these would be connected to bus 0x02 or higher.
> 
> Fix this by initializing the RC to a subordinate value of 0xff, which is
> not altering hardware behaviour in any way, but informs probing
> function pci_scan_bridge() later on which reads this value back from
> register.
> 
> Following nasty errors during boot are also fixed by this:
> 
> [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
> under [bus 01] (conflicts with (null) [bus 01])
> ...
> [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
> 0000:01 [bus 01]
> ...
> [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
> 0000:01 [bus 01]
> [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
> 05
> [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
> under [bus 01] (conflicts with (null) [bus 01])
> [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
> bridge 0000:01 [bus 01]
> 
> Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> parent")
> Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
> Tested-by: Niklas Cassel <niklas.cassel@axis.com>
> Cc: Binghui Wang <wangbinghui@hisilicon.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Jianguo Sun <sunjianguo1@huawei.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
> Cc: Minghuan Lian <minghuan.Lian@freescale.com>
> Cc: Mingkai Hu <mingkai.hu@freescale.com>
> Cc: Murali Karicheri <m-karicheri2@ti.com>
> Cc: Pratyush Anand <pratyush.anand@gmail.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Roy Zang <tie-fei.zang@freescale.com>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Xiaowei Song <songxiaowei@hisilicon.com>
> Cc: Zhou Wang <wangzhou1@hisilicon.com>
> ---
>  drivers/pci/dwc/pcie-designware-host.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

I would appreciate some testing from dwc host maintainers so that
we can merge this patch, it is a bug fix that should be merged as
soon as possible, please help Koen test it and provide feedback
on the list.

Lorenzo

> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index bf558df5b7b3..2b5470173196 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -616,7 +616,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	/* setup bus numbers */
>  	val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
>  	val &= 0xff000000;
> -	val |= 0x00010100;
> +	val |= 0x00ff0100;
>  	dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
>  
>  	/* setup command register */
> -- 
> 2.7.4
>
Mika Westerberg - Feb. 5, 2018, 8:06 p.m.
On Mon, Feb 05, 2018 at 07:14:21PM +0000, Lorenzo Pieralisi wrote:
> On Mon, Jan 15, 2018 at 10:36:08AM +0100, Koen Vandeputte wrote:
> > The subordinate value indicates the highest bus number which can be
> > reached downstream though a certain device.
> > 
> > Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> > parent")
> > ensures that downstream devices cannot assign busnumbers higher than the
> > upstream device subordinate number, which was indeed illogical.
> > 
> > By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
> > value of 0x01.
> > 
> > Due to this combined with above commit, enumeration stops digging deeper
> > downstream as soon as bus num 0x01 has been assigned, which is always
> > the case for a bridge device.
> > 
> > This results in all devices behind a bridge bus to remain undetected, as
> > these would be connected to bus 0x02 or higher.
> > 
> > Fix this by initializing the RC to a subordinate value of 0xff, which is
> > not altering hardware behaviour in any way, but informs probing
> > function pci_scan_bridge() later on which reads this value back from
> > register.
> > 
> > Following nasty errors during boot are also fixed by this:
> > 
> > [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
> > under [bus 01] (conflicts with (null) [bus 01])
> > ...
> > [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
> > 0000:01 [bus 01]
> > ...
> > [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
> > 0000:01 [bus 01]
> > ...
> > [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
> > 0000:01 [bus 01]
> > [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
> > 05
> > [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
> > under [bus 01] (conflicts with (null) [bus 01])
> > [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
> > bridge 0000:01 [bus 01]
> > 
> > Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
> > parent")
> > Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
> > Tested-by: Niklas Cassel <niklas.cassel@axis.com>
> > Cc: Binghui Wang <wangbinghui@hisilicon.com>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> > Cc: Jianguo Sun <sunjianguo1@huawei.com>
> > Cc: Jingoo Han <jingoohan1@gmail.com>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>
> > Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
> > Cc: Minghuan Lian <minghuan.Lian@freescale.com>
> > Cc: Mingkai Hu <mingkai.hu@freescale.com>
> > Cc: Murali Karicheri <m-karicheri2@ti.com>
> > Cc: Pratyush Anand <pratyush.anand@gmail.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> > Cc: Roy Zang <tie-fei.zang@freescale.com>
> > Cc: Shawn Guo <shawn.guo@linaro.org>
> > Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
> > Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > Cc: Xiaowei Song <songxiaowei@hisilicon.com>
> > Cc: Zhou Wang <wangzhou1@hisilicon.com>
> > ---
> >  drivers/pci/dwc/pcie-designware-host.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> I would appreciate some testing from dwc host maintainers so that
> we can merge this patch, it is a bug fix that should be merged as
> soon as possible, please help Koen test it and provide feedback
> on the list.

BTW, this should have a stable tag so that it gets backported to stable
kernels. I guess whoever is applying the patch can add it so no need for
another revision.
Fabio Estevam - Feb. 5, 2018, 10:12 p.m.
Hi Mika

On Mon, Feb 5, 2018 at 6:06 PM, Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:

> BTW, this should have a stable tag so that it gets backported to stable
> kernels. I guess whoever is applying the patch can add it so no need for
> another revision.

I agree it needs to be backported to stable as I adapted this patch to
4.9 and it fixed the issue there.

However the Fixes lines mentions commit a20c7f36bd3d, which only
appears in 4.15, so that is confusing for backporting to older
kernels.
Sebastian Reichel - Feb. 6, 2018, 10:44 a.m.
Hi,

This patch fixes network support for GE Healthcare B850v3, which has
two network cards attached to a PCIe switch and is

Tested-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>

-- Sebastian
Fabio Estevam - Feb. 14, 2018, 3:41 p.m.
Hi Lucas and Richard,

On Mon, Feb 5, 2018 at 5:14 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> On Mon, Jan 15, 2018 at 10:36:08AM +0100, Koen Vandeputte wrote:
>> The subordinate value indicates the highest bus number which can be
>> reached downstream though a certain device.
>>
>> Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
>> parent")
>> ensures that downstream devices cannot assign busnumbers higher than the
>> upstream device subordinate number, which was indeed illogical.
>>
>> By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a
>> value of 0x01.
>>
>> Due to this combined with above commit, enumeration stops digging deeper
>> downstream as soon as bus num 0x01 has been assigned, which is always
>> the case for a bridge device.
>>
>> This results in all devices behind a bridge bus to remain undetected, as
>> these would be connected to bus 0x02 or higher.
>>
>> Fix this by initializing the RC to a subordinate value of 0xff, which is
>> not altering hardware behaviour in any way, but informs probing
>> function pci_scan_bridge() later on which reads this value back from
>> register.
>>
>> Following nasty errors during boot are also fixed by this:
>>
>> [    0.459145] pci_bus 0000:02: busn_res: can not insert [bus 02-ff]
>> under [bus 01] (conflicts with (null) [bus 01])
>> ...
>> [    0.464515] pci_bus 0000:03: [bus 03] partially hidden behind bridge
>> 0000:01 [bus 01]
>> ...
>> [    0.464892] pci_bus 0000:04: [bus 04] partially hidden behind bridge
>> 0000:01 [bus 01]
>> ...
>> [    0.466488] pci_bus 0000:05: [bus 05] partially hidden behind bridge
>> 0000:01 [bus 01]
>> [    0.466506] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to
>> 05
>> [    0.466517] pci_bus 0000:02: busn_res: can not insert [bus 02-05]
>> under [bus 01] (conflicts with (null) [bus 01])
>> [    0.466534] pci_bus 0000:02: [bus 02-05] partially hidden behind
>> bridge 0000:01 [bus 01]
>>
>> Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in
>> parent")
>> Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
>> Tested-by: Niklas Cassel <niklas.cassel@axis.com>
>> Cc: Binghui Wang <wangbinghui@hisilicon.com>
>> Cc: Bjorn Helgaas <bhelgaas@google.com>
>> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
>> Cc: Jianguo Sun <sunjianguo1@huawei.com>
>> Cc: Jingoo Han <jingoohan1@gmail.com>
>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Cc: Lucas Stach <l.stach@pengutronix.de>
>> Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
>> Cc: Minghuan Lian <minghuan.Lian@freescale.com>
>> Cc: Mingkai Hu <mingkai.hu@freescale.com>
>> Cc: Murali Karicheri <m-karicheri2@ti.com>
>> Cc: Pratyush Anand <pratyush.anand@gmail.com>
>> Cc: Richard Zhu <hongxing.zhu@nxp.com>
>> Cc: Roy Zang <tie-fei.zang@freescale.com>
>> Cc: Shawn Guo <shawn.guo@linaro.org>
>> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
>> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
>> Cc: Xiaowei Song <songxiaowei@hisilicon.com>
>> Cc: Zhou Wang <wangzhou1@hisilicon.com>
>> ---
>>  drivers/pci/dwc/pcie-designware-host.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> I would appreciate some testing from dwc host maintainers so that
> we can merge this patch, it is a bug fix that should be merged as
> soon as possible, please help Koen test it and provide feedback
> on the list.

Is it possible for you to test this patch?

Thanks
Lucas Stach - Feb. 14, 2018, 3:49 p.m.
Am Mittwoch, den 14.02.2018, 13:41 -0200 schrieb Fabio Estevam:
> Hi Lucas and Richard,
> 
> On Mon, Feb 5, 2018 at 5:14 PM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
[...]
> > I would appreciate some testing from dwc host maintainers so that
> > we can merge this patch, it is a bug fix that should be merged as
> > soon as possible, please help Koen test it and provide feedback
> > on the list.
> 
> Is it possible for you to test this patch?

I did not test myself, but a Pengutronix colleague did and reported it
did fix the bus scanning issues, while not introducing any obvious
issues.

Acked-by: Lucas Stach <l.stach@pengutronix.de>

Regards,
Lucas

Patch

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index bf558df5b7b3..2b5470173196 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -616,7 +616,7 @@  void dw_pcie_setup_rc(struct pcie_port *pp)
 	/* setup bus numbers */
 	val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
 	val &= 0xff000000;
-	val |= 0x00010100;
+	val |= 0x00ff0100;
 	dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
 
 	/* setup command register */