[RFC,4/4] drm/nouveau: Add SLCG clockgating for Kepler2

Commit Message

Lyude Paul Jan. 15, 2018, 10:06 p.m. UTC

That's right, there's still more power saving to go! This enables the
third level of clockgating, SLCG (this stands for... we don't actually
know what this stands for yet :\). While the register values look a
little different, programming them is exactly the same as BLCG.
Additionally, it should be noted that SLCG was added starting with
kepler2, previous generations have no SLCG.

SLCG can be enabled with the nouveau config option, NvPmEnableGating=3

Signed-off-by: Lyude Paul <[e-mail]>
---
 .../gpu/drm/nouveau/include/nvkm/subdev/therm.h    |   1 +
 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c     | 108 +++++++++++++++++++++
 drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c   |   3 +-
 3 files changed, 111 insertions(+), 1 deletion(-)

Patch

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
index 4b49561415ef..ba50207791e0 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
@@ -50,6 +50,7 @@  enum nvkm_therm_clkgate_level {
 	NVKM_THERM_CLKGATE_NONE = 0,
 	NVKM_THERM_CLKGATE_CG, /* basic clockgating */
 	NVKM_THERM_CLKGATE_BLCG,
+	NVKM_THERM_CLKGATE_SLCG,
 };
 
 struct nvkm_therm_clkgate_init {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
index d26bfa3062e6..35ad52529c9a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
@@ -187,6 +187,89 @@  gk110_clkgate_blcg_init_gpc_mp_0[] = {
 	{}
 };
 
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_main_0[] = {
+	{ 0x4041f4, 1, 0x00000000 },
+	{ 0x409894, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_unk_0[] = {
+	{ 0x406004, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_sked_0[] = {
+	{ 0x407004, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_ctxctl_0[] = {
+	{ 0x41a894, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_unk_0[] = {
+	{ 0x418504, 1, 0x00000000 },
+	{ 0x41860c, 1, 0x00000000 },
+	{ 0x41868c, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_esetup_0[] = {
+	{ 0x41882c, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_zcull_0[] = {
+	{ 0x418974, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_l1c_0[] = {
+	{ 0x419cd8, 2, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_unk_1[] = {
+	{ 0x419c74, 1, 0x00000000 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_mp_0[] = {
+	{ 0x419fd4, 1, 0x00004a4a },
+	{ 0x419fdc, 1, 0x00000014 },
+	{ 0x419fe4, 1, 0x00000000 },
+	{ 0x419ff4, 1, 0x00001724 },
+	{}
+};
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_gpc_ppc_0[] = {
+	{ 0x41be2c, 1, 0x00000000 },
+	{}
+};
+
+/* TODO: add ELPG here */
+
+const struct nvkm_therm_clkgate_init
+gk110_clkgate_slcg_init_pcounter_0[] = {
+	{ 0x1be018, 1, 0x000001ff },
+	{ 0x1bc018, 1, 0x000001ff },
+	{ 0x1b8018, 1, 0x000001ff },
+	{ 0x1b4124, 1, 0x00000000 },
+	{}
+};
+
 const struct nvkm_therm_clkgate_pack
 gk110_clkgate_pack[] = {
 	{
@@ -220,6 +303,31 @@  gk110_clkgate_pack[] = {
 			NULL,
 		},
 	},
+	{
+		NVKM_THERM_CLKGATE_SLCG,
+		(const struct nvkm_therm_clkgate_init*[]) {
+			gk110_clkgate_slcg_init_main_0,
+			gk110_clkgate_slcg_init_unk_0,
+			gk110_clkgate_slcg_init_sked_0,
+			gk110_clkgate_slcg_init_gpc_ctxctl_0,
+			gk110_clkgate_slcg_init_gpc_unk_0,
+			gk110_clkgate_slcg_init_gpc_esetup_0,
+			gk110_clkgate_slcg_init_gpc_zcull_0,
+			gk110_clkgate_slcg_init_gpc_l1c_0,
+			gk110_clkgate_slcg_init_gpc_unk_1,
+			gk110_clkgate_slcg_init_gpc_mp_0,
+			gk110_clkgate_slcg_init_gpc_ppc_0,
+			NULL,
+		},
+	},
+	/* TODO: ELPG programming happens -here- */
+	{
+		NVKM_THERM_CLKGATE_SLCG,
+		(const struct nvkm_therm_clkgate_init*[]) {
+			gk110_clkgate_slcg_init_pcounter_0,
+			NULL
+		},
+	},
 	{}
 };
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
index ee028d099f6a..587dcc7444a7 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
@@ -332,6 +332,7 @@  nvkm_therm_clkgate_oneinit(struct nvkm_therm *therm)
 	switch (therm->clkgate_level) {
 	case NVKM_THERM_CLKGATE_CG:   clkgate_str = "CG"; break;
 	case NVKM_THERM_CLKGATE_BLCG: clkgate_str = "BLCG"; break;
+	case NVKM_THERM_CLKGATE_SLCG: clkgate_str = "SLCG"; break;
 	default: BUG();
 	}
 
@@ -449,7 +450,7 @@  nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device,
 		clamp((int)nvkm_longopt(device->cfgopt,
 					"NvPmEnableGating",
 					NVKM_THERM_CLKGATE_NONE),
-		      NVKM_THERM_CLKGATE_NONE, NVKM_THERM_CLKGATE_BLCG);
+		      NVKM_THERM_CLKGATE_NONE, NVKM_THERM_CLKGATE_SLCG);
 }
 
 int