@@ -37,7 +37,8 @@
(BIT(I915_SAMPLE_BUSY) | \
BIT(I915_SAMPLE_WAIT) | \
BIT(I915_SAMPLE_SEMA) | \
- BIT(I915_SAMPLE_QUEUED))
+ BIT(I915_SAMPLE_QUEUED) | \
+ BIT(I915_SAMPLE_SUBMITTED))
#define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
@@ -226,6 +227,11 @@ static void engines_sample(struct drm_i915_private *dev_priv)
update_sample(&engine->pmu.sample[I915_SAMPLE_QUEUED],
1 / I915_SAMPLE_QUEUED_SCALE,
engine->queued);
+
+ if (engine->pmu.enable & BIT(I915_SAMPLE_SUBMITTED))
+ update_sample(&engine->pmu.sample[I915_SAMPLE_SUBMITTED],
+ 1 / I915_SAMPLE_SUBMITTED_SCALE,
+ atomic_read(&engine->submitted));
}
if (fw)
@@ -304,6 +310,7 @@ engine_event_status(struct intel_engine_cs *engine,
case I915_SAMPLE_BUSY:
case I915_SAMPLE_WAIT:
case I915_SAMPLE_QUEUED:
+ case I915_SAMPLE_SUBMITTED:
break;
case I915_SAMPLE_SEMA:
if (INTEL_GEN(engine->i915) < 6)
@@ -415,7 +422,8 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
val = engine->pmu.sample[sample].cur;
}
- if (sample == I915_SAMPLE_QUEUED)
+ if (sample == I915_SAMPLE_QUEUED ||
+ sample == I915_SAMPLE_SUBMITTED)
val = div_u64(val, FREQUENCY);
} else {
switch (event->attr.config) {
@@ -790,6 +798,8 @@ create_event_attributes(struct drm_i915_private *i915)
__engine_event(I915_SAMPLE_WAIT, "wait"),
__engine_event_scale(I915_SAMPLE_QUEUED, "queued",
__stringify(I915_SAMPLE_QUEUED_SCALE)),
+ __engine_event_scale(I915_SAMPLE_SUBMITTED, "submitted",
+ __stringify(I915_SAMPLE_SUBMITTED_SCALE)),
};
unsigned int count = 0;
struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
@@ -379,7 +379,7 @@ struct intel_engine_cs {
*
* Our internal timer stores the current counters in this field.
*/
-#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_QUEUED + 1)
+#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SUBMITTED + 1)
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
/**
* @busy_stats: Has enablement of engine stats tracking been
@@ -111,10 +111,12 @@ enum drm_i915_pmu_engine_sample {
I915_SAMPLE_BUSY = 0,
I915_SAMPLE_WAIT = 1,
I915_SAMPLE_SEMA = 2,
- I915_SAMPLE_QUEUED = 3
+ I915_SAMPLE_QUEUED = 3,
+ I915_SAMPLE_SUBMITTED = 4,
};
#define I915_SAMPLE_QUEUED_SCALE 1e-2 /* No braces please. */
+#define I915_SAMPLE_SUBMITTED_SCALE 1e-2 /* No braces please. */
#define I915_PMU_SAMPLE_BITS (4)
#define I915_PMU_SAMPLE_MASK (0xf)
@@ -139,6 +141,9 @@ enum drm_i915_pmu_engine_sample {
#define I915_PMU_ENGINE_QUEUED(class, instance) \
__I915_PMU_ENGINE(class, instance, I915_SAMPLE_QUEUED)
+#define I915_PMU_ENGINE_SUBMITTED(class, instance) \
+ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SUBMITTED)
+
#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)