| Message ID | 20180119144152.17224-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> On Fri, Jan 19, 2018 at 6:41 AM, Ville Syrjala < ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Let's document why we claim hsub==8,vsub==16 for CCS. > > v2: Replace my explanation with Jason's > > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: Ben Widawsky <ben@bwidawsk.net> > Cc: Jason Ekstrand <jason@jlekstrand.net> > Cc: Daniel Stone <daniels@collabora.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 91f3c0a64596..8d0d5d8753c0 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2387,6 +2387,20 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t > fb_modifier) > } > } > > +/* > + * From the Sky Lake PRM: > + * "The Color Control Surface (CCS) contains the compression status of > + * the cache-line pairs. The compression state of the cache-line pair > + * is specified by 2 bits in the CCS. Each CCS cache-line represents > + * an area on the main surface of 16 x16 sets of 128 byte Y-tiled > + * cache-line-pairs. CCS is always Y tiled." > + * > + * Since cache line pairs refers to horizontally adjacent cache lines, > + * each cache line in the CCS corresponds to an area of 32x16 cache > + * lines on the main surface. Since each pixel is 4 bytes, this gives > + * us a ratio of one byte in the CCS for each 8x16 pixels in the > + * main surface. > + */ > static const struct drm_format_info ccs_formats[] = { > { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, > { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, > -- > 2.13.6 > >
On Sat, Jan 20, 2018 at 09:39:13AM -0800, Jason Ekstrand wrote: > Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Thanks for the comment and review ;) Patches 1-6 have now been pushed to dinq. > > On Fri, Jan 19, 2018 at 6:41 AM, Ville Syrjala < > ville.syrjala@linux.intel.com> wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Let's document why we claim hsub==8,vsub==16 for CCS. > > > > v2: Replace my explanation with Jason's > > > > Cc: Daniel Vetter <daniel@ffwll.ch> > > Cc: Ben Widawsky <ben@bwidawsk.net> > > Cc: Jason Ekstrand <jason@jlekstrand.net> > > Cc: Daniel Stone <daniels@collabora.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 91f3c0a64596..8d0d5d8753c0 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -2387,6 +2387,20 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t > > fb_modifier) > > } > > } > > > > +/* > > + * From the Sky Lake PRM: > > + * "The Color Control Surface (CCS) contains the compression status of > > + * the cache-line pairs. The compression state of the cache-line pair > > + * is specified by 2 bits in the CCS. Each CCS cache-line represents > > + * an area on the main surface of 16 x16 sets of 128 byte Y-tiled > > + * cache-line-pairs. CCS is always Y tiled." > > + * > > + * Since cache line pairs refers to horizontally adjacent cache lines, > > + * each cache line in the CCS corresponds to an area of 32x16 cache > > + * lines on the main surface. Since each pixel is 4 bytes, this gives > > + * us a ratio of one byte in the CCS for each 8x16 pixels in the > > + * main surface. > > + */ > > static const struct drm_format_info ccs_formats[] = { > > { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, > > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, > > { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, > > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, > > -- > > 2.13.6 > > > >
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 91f3c0a64596..8d0d5d8753c0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2387,6 +2387,20 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) } } +/* + * From the Sky Lake PRM: + * "The Color Control Surface (CCS) contains the compression status of + * the cache-line pairs. The compression state of the cache-line pair + * is specified by 2 bits in the CCS. Each CCS cache-line represents + * an area on the main surface of 16 x16 sets of 128 byte Y-tiled + * cache-line-pairs. CCS is always Y tiled." + * + * Since cache line pairs refers to horizontally adjacent cache lines, + * each cache line in the CCS corresponds to an area of 32x16 cache + * lines on the main surface. Since each pixel is 4 bytes, this gives + * us a ratio of one byte in the CCS for each 8x16 pixels in the + * main surface. + */ static const struct drm_format_info ccs_formats[] = { { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },