diff mbox

drm/i915: apply phase pointer override on SNB+ too

Message ID 1311898032-6625-1-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes July 29, 2011, 12:07 a.m. UTC 
These bits moved around on SNB and above.

v2: again with the git send-email fail

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |    8 ++++++++
 drivers/gpu/drm/i915/intel_display.c |   29 ++++++++++++++++++++++++++++-
 2 files changed, 36 insertions(+), 1 deletions(-)

Comments

Keith Packard July 29, 2011, 5:28 p.m. UTC | #1 
On Thu, 28 Jul 2011 17:07:12 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> +#define _TRANSA_CHICKEN2	 0xf0064
> +#define _TRANSB_CHICKEN2	 0xf1064
> +#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> +#define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)
> +
> +#define SOUTH_CHICKEN1		0xc2000
> +#define  FDIA_PHASE_SYNC_SHIFT	18
> +#define  FDI_PHASE_SYNC_OVR_EN	(3)

How about

#define FDIA_PHASE_SYNC_OVERRIDE_SHIFT  19
#define FDIA_PHASE_SYNC_ENABLE_SHIFT    18
#define FDI_PHASE_SYNC_OVERRIDE(pipe) (1 << (FDIA_PHASE_SYNC_OVERRIDE_SHIFT - (pipe) * 2))
#define FDI_PHASE_SYNC_ENABLE(pipe)   (1 << (FDIA_PHASE_SYNC_ENABLE_SHIFT - (pipe) * 2))

defines instead?

Then use FDI_PHASE_SYNC_OVERRIDE(pipe) | FDI_PHASE_SYNC_ENABLE(pipe)

in the code.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..7261113 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3075,6 +3075,14 @@ 
 #define  TRANS_6BPC             (2<<5)
 #define  TRANS_12BPC            (3<<5)
 
+#define _TRANSA_CHICKEN2	 0xf0064
+#define _TRANSB_CHICKEN2	 0xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_AUTOTRAIN_GEN_STALL_DIS	(1<<31)
+
+#define SOUTH_CHICKEN1		0xc2000
+#define  FDIA_PHASE_SYNC_SHIFT	18
+#define  FDI_PHASE_SYNC_OVR_EN	(3)
 #define SOUTH_CHICKEN2		0xc2004
 #define  DPLS_EDP_PPS_FIX_DIS	(1<<0)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5609c06..65ead57 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2086,6 +2086,18 @@  static void intel_fdi_normal_train(struct drm_crtc *crtc)
 			   FDI_FE_ERRC_ENABLE);
 }
 
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+	flags |= FDI_PHASE_SYNC_OVR_EN << (FDIA_PHASE_SYNC_SHIFT - (pipe * 2));
+
+	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+	POSTING_READ(SOUTH_CHICKEN1);
+}
+
 /* The FDI link training functions for ILK/Ibexpeak. */
 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 {
@@ -2133,7 +2145,8 @@  static void ironlake_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
 			   FDI_RX_PHASE_SYNC_POINTER_EN);
-	}
+	} else if (HAS_PCH_CPT(dev))
+		cpt_phase_pointer_enable(dev, pipe);
 
 	reg = FDI_RX_IIR(pipe);
 	for (tries = 0; tries < 5; tries++) {
@@ -2461,6 +2474,18 @@  static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
 	}
 }
 
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+	flags &= ~(FDI_PHASE_SYNC_OVR_EN << (FDIA_PHASE_SYNC_SHIFT -
+					     (pipe * 2)));
+
+	I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+	I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+	POSTING_READ(SOUTH_CHICKEN1);
+}
 static void ironlake_fdi_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -2490,6 +2515,8 @@  static void ironlake_fdi_disable(struct drm_crtc *crtc)
 		I915_WRITE(FDI_RX_CHICKEN(pipe),
 			   I915_READ(FDI_RX_CHICKEN(pipe) &
 				     ~FDI_RX_PHASE_SYNC_POINTER_EN));
+	} else if (HAS_PCH_CPT(dev)) {
+		cpt_phase_pointer_disable(dev, pipe);
 	}
 
 	/* still set train pattern 1 */