| Message ID | 32142684-d5cf-035f-8401-86a36dcbafd6@cogentembedded.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | f3a54d6c17f5ec826ff81e4f9f35a11e63211c53 |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Sergei, On Fri, Feb 2, 2018 at 7:33 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, timer, > CPG, RST, and SYSC. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Thanks for your patch! > --- /dev/null > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi > @@ -0,0 +1,122 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for the r8a77980 SoC > + * > + * Copyright (C) 2018 Renesas Electronics Corp. > + * Copyright (C) 2018 Cogent Embedded, Inc. > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/renesas-cpg-mssr.h> I think you want to leave out the above #include, as it will go upstream through a different path (you're already using hardcoded clock numbers, assuming the same). With the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 2/5/2018 4:32 PM, Geert Uytterhoeven wrote: >> The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, timer, >> CPG, RST, and SYSC. >> >> Based on the original (and large) patch by Vladimir Barinov. >> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Thanks for your patch! > >> --- /dev/null >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi >> @@ -0,0 +1,122 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Device Tree Source for the r8a77980 SoC >> + * >> + * Copyright (C) 2018 Renesas Electronics Corp. >> + * Copyright (C) 2018 Cogent Embedded, Inc. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/renesas-cpg-mssr.h> > > I think you want to leave out the above #include, as it will go upstream > through a different path (you're already using hardcoded clock numbers, > assuming the same). I still need CPG_{CORE|MOD}. > With the above fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Sorry, I don't see anything worth fixing... > Gr{oetje,eeting}s, > > Geert MBR, Sergei
Hi Sergei, On Mon, Feb 5, 2018 at 2:48 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > On 2/5/2018 4:32 PM, Geert Uytterhoeven wrote: >>> The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, >>> timer, >>> CPG, RST, and SYSC. >>> >>> Based on the original (and large) patch by Vladimir Barinov. >>> >>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> >> >> Thanks for your patch! >> >>> --- /dev/null >>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi >>> @@ -0,0 +1,122 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Device Tree Source for the r8a77980 SoC >>> + * >>> + * Copyright (C) 2018 Renesas Electronics Corp. >>> + * Copyright (C) 2018 Cogent Embedded, Inc. >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/irq.h> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> +#include <dt-bindings/clock/renesas-cpg-mssr.h> >> >> I think you want to leave out the above #include, as it will go upstream >> through a different path (you're already using hardcoded clock numbers, >> assuming the same). > > I still need CPG_{CORE|MOD}. You're right. Please ignore my comment. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Mon, Feb 05, 2018 at 02:51:43PM +0100, Geert Uytterhoeven wrote: > Hi Sergei, > > On Mon, Feb 5, 2018 at 2:48 PM, Sergei Shtylyov > <sergei.shtylyov@cogentembedded.com> wrote: > > On 2/5/2018 4:32 PM, Geert Uytterhoeven wrote: > >>> The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, > >>> timer, > >>> CPG, RST, and SYSC. > >>> > >>> Based on the original (and large) patch by Vladimir Barinov. > >>> > >>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > >>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > >> > >> > >> Thanks for your patch! > >> > >>> --- /dev/null > >>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi > >>> @@ -0,0 +1,122 @@ > >>> +// SPDX-License-Identifier: GPL-2.0 > >>> +/* > >>> + * Device Tree Source for the r8a77980 SoC > >>> + * > >>> + * Copyright (C) 2018 Renesas Electronics Corp. > >>> + * Copyright (C) 2018 Cogent Embedded, Inc. > >>> + */ > >>> + > >>> +#include <dt-bindings/interrupt-controller/irq.h> > >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> > >>> +#include <dt-bindings/clock/renesas-cpg-mssr.h> > >> > >> I think you want to leave out the above #include, as it will go upstream > >> through a different path (you're already using hardcoded clock numbers, > >> assuming the same). > > > > I still need CPG_{CORE|MOD}. > > You're right. Please ignore my comment. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks, applied.
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a77980 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/ { + compatible = "renesas,r8a77980"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc 5>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller { + compatible = "cache"; + power-domains = <&sysc 21>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77980-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77980-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77980-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc 32>; + resets = <&cpg 408>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; +};